Yuta Tanimoto

Compact Modeling of the Transient Carrier Trap/Detrap Characteristics in Polysilicon TFTs

An investigation of the carrier trapping influence on device characteristics in poly-Si thin-film transistors (TFTs) is reported. Particular focus is laid on the transient characteristics, which is influenced by the carrier trapping during the device operation. On the basis of these features, a compact model for TFT-circuit simulation has been developed, which considers the dynamically changing time constant of the carrier trapping in the framework of a complete surface-potential description, thus enabling modeling the dynamically varying trapped carrier density. The compact model is verified against measured characteristics of repeated switching.

Power-Loss Prediction of High-Voltage SiC- mosfet Circuits With Compact Model Including Carrier-Trap Influences

The paper aims at clarifying the carrier-trapping influence on the electrical characteristics of silicon carbide (SiC) power MOSFETs and its inclusion in the simulation of SiC power mosfet-based circuits. Special focus is given on the degradation of the switching characteristics due to carrier trapping at SiC/SiO2 interface defects. A compact SiC power mosfet model, considering the trap density in the framework of a complete surface-potential description, has been developed by for accurate circuit simulation including power-loss prediction. The carrier trapping is verified to cause a switching delay, which results in switching loss increase. To achieve low power loss, trap-density reduction is shown to be vital. The maximum allowable trap density, which does not affect switching power loss, is discussed.

Analysis of GaN-HEMTs switching characteristics for power applications with compact model including parasitic contributions

In this paper, we report a newly developed compact model HiSIM-GaN [Hiroshima University STARC IGFET Model for GaN high electron mobility transistors (HEMTs)] including a capacitance model, which accurately captures the contributions originating from the devices field plate (FP) structure. The capabilities of the reported model are demonstrated by reproduction of the measured power efficiency of a boost converter circuit, enabled through separate extraction of the parasitic FP contributions. In addition, physical trap-density modeling is verified to be also of key importance for accurate prediction of the power efficiency.

Compact modeling of GaN HEMT based on device-internal potential distribution

A compact model of GaN HEMT is developed, which solves the Poisson equations explicitly. The model includes all possible charges induced within the device including the trap density. It is verified that the model can reproduce all 2D-device simulation results accurately. In particular, the operation frequency dependence of the current collapse can also be captured accurately by adjusting the trap time constant.

Compact modeling of carrier trapping for accurate prediction of frequency dependent circuit operation

We have investigated the influence of carrier traps on device characteristics in TFTs. In particular, our focus was given on transient characteristics influenced by carrier trapping during device operations. A compact model for circuit simulation of TFTs has been developed by considering the time constant of the trapping. The model was verified with measured frequency dependent TFT characteristics.

Analysis of GaN high electron mobility transistor switching characteristics for high-power applications with HiSIM-GaN compact model

This paper presents a newly developed compact model HiSIM-GaN [Hiroshima University STARC IGFET Model for GaN high electron mobility transistors (HEMTs)]. The developed model includes two specific features of GaN-HEMT to reproduce the power efficiency accurately. One is the two-dimensional electron gas induced at the heterojunction, which is modeled by considering the potential distribution across the junction including the trap density contribution. The second feature is the field plate, which is introduced to delocalize the electric-field peak that occurs at the electrode edge. Using HiSIM-GaN, device characteristics have been simulated. It is demonstrated that measured DC/AC characteristics are well reproduced with the developed model. The model has also been applied to analyze circuit characteristics of a boost converter. It is shown that the waveform is well reproduced by considering one half of the trap density extracted with measured DC characteristics due to the time constant of trap events. Furthermore, it is verified that the power efficiency as a function of the load current is predicted within an accuracy of 1%. Influence of the trap density and the field plate on circuit performances is also discussed.

Analysis of printed organic MOSFET characteristics with a focus on the temperature dependence

An experimental and theoretical investigation of the device characteristics of printed organic MOSFETs with a focus on the temperature dependence is reported. In particular, an anomalous behavior of the temperature dependence of the I ds–V gs characteristic is observed, which is found to be increased at higher temperature in MOSFETs fabricated with the printing technology. Our analysis suggests that the temperature dependence of the trap density and the carrier transport mechanism are the causes for this anomalous increase at higher temperature. The results obtained with the compact model HiSIM-Organic, developed based on the physics of carrier dynamics in organic materials, confirm these conclusions. Improving stable characteristics in circuit applications are demonstrated to be achievable at higher temperatures, due to these anomalous properties of organic MOSFETs fabricated by applying the printing technology.

Modeling of reverse recovery effect for embedded diode in SJ MOSFET

This investigation aims at developing a compact model for the embedded diode in Super-Junction MOSFETs applicable for more than 500V bias conditions. It is demonstrated that the reverse-recovery effect is different from the conventional stand-alone pin diode. The reason is the extension of the depletion at the additional p/n junction in the Super-Junction MOSFET under reverse bias applications. The depletion region prevents the current flow and thus forcing the rapid charge dissipation from the device. We have developed an embedded diode model on the basis of HiSIM-Diode originally developed for the conventional pin diode.

Consistent simulation of dynamic carrier trap/detrap effects on circuit performance

This paper summarizes investigations for the carrier-trapping influence on electric characteristics of MOSFETs. Particular focus is given on the transient characteristics, which is affected by the time constant of the carrier trapping during the device operation. For the purpose a compact model has been developed for circuit simulation by considering the dynamic trap/detrap feature in the framework of the complete surface-potential description in HiSIM. It is demonstrated that the trap-density model considers the trap/detrap time constant enables to simulate not only frequency dependent switching characteristics accurately but also long-term device degradation.