Ali Asghar Vatanjou

Ultra-low voltage adders in 28 nm FDSOI exploring poly-biasing for device sizing

Balancing the PMOS/NMOS strength ratio is a key issue to maximize the noise margin, and hence, functional yield of CMOS logic gates in the subthreshold region. In this work, the PMOS/NMOS strength ratio was balanced using a poly-biasing technique in conjunction with back-gate biasing provided in a 28 nm fully depleted silicon on insulator (FDSOI) technology. A 32-bit adder based on minority-3 (min-3) gates and a 16-bit adder based on Boolean gates have been implemented. Chip measurement results show highly energy efficient adders, so that the 32-bit and 16-bit adders achieved minimum energy point (MEP) of 21.5 fJ at 300 mV and 12.62 fJ at 250 mV, respectively. In comparison to adders reported in other works in the same technology, the energy per 1-bit addition of the 32-bit adder is improved by 35% and for the 16-bit adder this improvement in energy consumption is 23%. The designed adders were functional down to a supply voltage of 110 mV. Additionally, the minimum Vdd of the 32-bit adder decreased to 79 mV by applying a reverse back bias voltage to the PMOS devices.

Comparative analysis of flip-flop architectures for subthreshold applications in 28nm FDSOI

Nine D flip-flop architectures were implemented in 28nm FDSOI at a target, subthreshold, supply voltage of 200mV. The goal was to identify promising D flip-flops for ultra low power applications. The pass gate flip-flop was implemented using 49% of the S2CFFs area and was functional at the lowest operating voltage of 65mV in the typical process corner. At the targeted supply voltage of 200mV the racefree DFF gives the best functional yield of 99.8%. The flip-flops having the shortest D-Q delays were the PowerPC 603 and the transmission gate D flip-flop. These also had the lowest power delay products of 52.08aJ and 61.09aJ respectively.

Exploiting short channel effects and multi-Vt technology for increased robustness and reduced energy consumption, with application to a 16-bit subthreshold adder implemented in 65 nm CMOS

When using standard multi-Vt CMOS processes when making logic gates, often for example Low-Vt (LVT), or Standard-Vt (SVT) or High-Vt (HVT) transistors are used within one and the same basic logic building block, like for example a NAND or NOR circuit. We show, to the contrary, how a combination of different types within a single logic circuit may be exploited to reduce energy consumption and increase robustness towards process variations. Additionaly, Reverse Short Channel Effects (RSCE) are exploited by using non-minimum gate lengths for increased robustness agains process variations. Also, a recently proposed technique using very regular layouts accompanying the above mentioned techniques in a 16-bit adder implemented in 65 nm CMOS. Chip measurements using Sub-/Nearthreshold supply voltages demonstrate the functionality of the adder for a voltage range of 119 mV to 350 mV. Simulations show that by increasing gate lengths to 200 nm instead of the minimum 60 nm, may increase the footprint area of logic gates by only 12 %, while at the same time reducing probability of failure by up to several orders of magnitude. Simultaneously, energy per operation is reduced, when compared to conventional design methods using minimum, or relatively short, gate lengths.

Energy efficient sub/near-threshold ripple-carry adder in standard 65 nm CMOS

This manuscript includes chip measurements for a 32-bit Ripple-Carry Adder (“RCA”), demonstrating functionality for a supply voltage (“Vdd”) down to 84 mV. The low Vdd might be the lowest reported for comparable CMOS circuitry, not depending on special schmitt-trigger based logic or body biasing. Two 32-bit ripple-carry adders are implemented in 65 nm CMOS, having all gate lengths of 60 nm and 80 nm, respectively. The implementation having 80 nm gate lengths exploits secondary effects like the Reverse Short Channel Effect (“RSCE”) to provide lower energy per operation, compared to the 60 nm implementation, when operated down to subthreshold supply voltages. Dimensioning for symmetric noise margins, and using minority-3 circuits and inverters only, with regular layouts, contribute to the ultra low Vdd potential. According to simulations, the energy per operation could be down to about 1.5 fJ/bit for the implementation, based on L = 80 nm. For delays in the 20 ns to 110 ns range, the energy consumption for the RCA having L = 60 nm, was from 18.5 to 47 % higher than the RCA having L = 80 nm. The area was 9.7 % less for the L = 80 nm implementation, compared to the L = 60 nm RCA.

Extended Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28 nm FD-SOI ☆

Abstract Nine D-type Flip-Flop (DFF) architectures were implemented in 28 nm FDSOI at a target, subthreshold, supply voltage of 200 mV. The goal was to identify promising DFFs for ultra low power applications. The single-transistor pass gate DFF, the PowerPC 603 DFF and the C 2 MOS DFF are considered to be the overall best candidates of the nine. The pass gate DFF had the lowest energy consumption per cycle for frequencies lower than 500 kHz and for supply voltages below 400 mV. It was implemented with the smallest physical footprint and it proved to be functional down to the lowest operating voltage of 65 mV in the typical process corner. During Monte Carlo (MC) process and mismatch simulations it was also found that the pass gate DFF is least prone to variations in both minimal setup- and minimal hold-time. Race conditions, during mismatch variations, occurred for the flip-flop that is constructed from NAND and inverter based multiplexers. The pass gate DFF is outperformed slightly when it comes to D-Q-based power-delay product and more significantly when it comes to the maximum clock frequency. The flip-flops having the shortest D-Q delays were the PowerPC 603 and the transmission gate D flip-flop, these also had the lowest D-Q-based power-delay of 26% and 30% respectively of that of the worst-case S 2 CFF power-delay product.

28 nm UTBB-FDSOI energy efficient and variation tolerant custom digital-cell library with application to a subthreshold MAC block

This paper presents the design of digital logic cells for subthreshold applications using 28 nm ultra-thin body and box fully depleted silicon on insulator technology. The sizing approach relies on balancing pull-up/pull-down networks (PUN/PDN) strength ratio by applying an additional forward back-gate biasing (FBB) voltage to the back-gate of PMOS transistors. The minimum width of PMOS and NMOS transistors have been chosen by taking the narrow width effect into account. Moreover, to increase the functional yield of the logic cells, a trade-off has been made between Ion/Ioff ratio and energy consumption through increasing the channel length by 4 nm. Energy consumption of logic gates analyzed using ring-oscillators consisting of basic logic gates. It has been shown that balancing logic gates through applying an additional FBB to the PMOS back-gate instead of up-sizing PUN results in 30% lower energy consumption in ring-oscillators. An 8-bit multiply-accumulate (MAC) block was synthesized using the fully customized logic cells with asymmetric back-gate biasing. Compared to a state-of-the art MAC, the energy consumption of our MAC was improved by 21% at a relatively high speed (147 MHz).