Tsuyoshi Shibata

The optimizations of resist shrink process using track-based technology

The development of double patterning processes/schemes are widely in progress for 2x nm node and beyond by using 193nm immersion lithography. It is realized that a resist shrink step is necessary in many double patterning process cases due to the resolution limit of the 193nm immersion exposure tool. As the development work progresses into the mass-product transition phase, the requirement for technical performances has become more difficult to be achieved by existing resist shrink technologies. In order to overcome these difficulties, we have developed wet slimming process based on our coater/developer technologies including the platform. The process is optimized for CD uniformity and defectivity. The process also has good robustness to the various possible resist materials and/or exposure conditions used by industry. In this paper, we introduce the scheme of wet slimming process together with basic performance data such as CD controllability, CD uniformity, defectivity and I-D bias. The evaluation data on actual double patterning processed wafers is reported as well.

CD uniformity improvement for double-patterning lithography (litho-litho-etch) using freezing process

After an analysis of the factors that causes critical dimension (CD) variation in the lithography process of the LLE (Litho-Litho-Etch) double-patterning technology that employs the freezing process, an optimum process for freezing the resist patterns to reduce the CD variation, which occurs after the 2nd litho process, was achieved. By optimizing the track parameters of freezing process, CD variation is likely to be reduced not only in the 1st resist pattern but also in the 2nd resist pattern. The optimum conditions were adopted to form patterns of 40 nm resist lines and spaces in the evaluations conducted in this paper. The formation result showed improvement of 3 sigma of the within-wafer CD uniformity of both the 1st resist pattern and the 2nd resist pattern, by about 13% and 46% respectively.

CDU Minimization at the 45nm node and beyond -Optical, Resist and Process Contributions to CD Control

As the industry transitions to the 45 nm node and beyond, requirements for critical dimension (CD) control are getting extremely aggressive. Current 45 nm node specifications call for 2 nm or better CD uniformity (CDU) on the gate level. For critical dimension control in this regime all measurable process effects must be closely monitored and controlled. This includes such effects as etch uniformity, scanner dose and focus consistency, post-exposure bake (PEB) plate uniformity, and incoming wafer variation such as wafer warpage. The problem is that as the number of significant contributors to CDU continues to increase; the number of parameters that can be used to control CDU has not. To better understand how to achieve these increasingly stringent CDU targets, the authors have explored how exposure and resist processing effects CD control. The goal of this work is to simulate how process parameters such as dose and PEB temperature can be used to effectively control CD, while minimizing unintended negative effects on thru pitch CD performance, MEEF, and other lithography process metrics. In addition to traditional lithography metrics, the effect these process changes have on CDU is simulated using a Monte Carlo technique.

Study of residue type defect formation mechanism and the effect of advanced defect reduction (ADR) rinse process

Residue type defect is one of yield detractors in lithography process. It is known that occurrence of the residue type defect is dependent on resist development process and the defect is reduced by optimized rinsing condition. However, the defect formation is affected by resist materials and substrate conditions. Therefore, it is necessary to optimize the development process condition by each mask level. Those optimization steps require a large amount of time and effort. The formation mechanism is investigated from viewpoint of both material and process. The defect formation is affected by resist material types, substrate condition and development process condition (D.I.W. rinse step). Optimized resist formulation and new rinse technology significantly reduce the residue type defect.

Non-topcoat process development for ArF immersion lithography

Mass production of 193-nm immersion lithography has been started. Top coat process is one of the practical solutions for applying the conventional dry ArF resists to achieve low material leaching and good scanning property, etc... At the present, the lithographic world requires non-topcoat process from the point of view of C.O.O. (cost of ownership), however there are still concerns that have to be revealed and solved. In order to achieve higher scan speed, the superior water repellent property is required at the surface of non-topcoat resist. On the other hand, the influence of water repellent surface property to the track process has to be considered. In this report, the considered items (coating, development, etc...) of the higher water repellent property in non-topcoat process were extracted. Material design for optimization of surface property with JSR non-topcoat resist and novel rinse method from process were proposed as solutions to the concerns. Optimization of surface property showed positive impact to the development and defect performance. The novel rinse method ADR which has been developed by Tokyo Electron showed superior availability to reduction of blob type defect.

Resist dispense system for further defect reduction

As pattern size becomes smaller, requirement for defect reduction is getting higher and higher. It is known that defects occur in various steps of lithography process. In this study, we focus on defects related to the resist dispense system. Of those defects, the most typical is bridge type defect which caused by foreign substances contained in resist film. The source of those is considered to be insoluble substances, such as resist gels, in resist liquid. So far, the conventional countermeasure has been the development of resist line filters (optimization of materials, shrinking of pore size, and so on). But, according to the recent reports and our experimental result, we can say that not only filter type but also filtration condition has certain influence on bridge type defect generation. In this study, we examine the influences of resist dispense system and its parameters on bridge type defect generation. This paper provides some experimental data and introduces our approaches to the optimization of resist dispense system and its effects.

Process-induced bias: a study of resist design and process implications

Critical dimension uniformity (CDU) has both across field and across wafer components. CD error generated by across wafer etching non-uniformity and other process variations can have a significant impact on CDU. To correct these across wafer variations, compensation by exposure dose and/or PEB temperature, have been proposed. These compensation strategies often focus on a specific structure without evaluating how process compensation impacts the CDU of all structures to be printed in a given design. In a previous study, the authors evaluated the relative merits of across wafer dose and PEB temperature compensation on the process induced CD bias and CDU. For the process studied, both metrics demonstrated that using PEB temperature to control across wafer CD variation was preferable to using dose compensation. The previous study was limited to a single resist and variations to track and scanner processing were kept to a minimum. Further examination of additional resist materials has indicated that significant variation in dose and PEB temperature induced CD biases exist from material to material. It is the goal of this work to understand how resist design, as well as track and scanner processing, impact process induced bias (PIB). This is accomplished by analyzing full resist models for a range of resists that exhibit different dose and PEB temperature PIB behavior. From these models, the primary resist design contributors to PIB are isolated. A sensitivity analysis of the primary resist design as well as track and scanner processing effects will also be simulated and presented.

Process-induced bias: a study of resist design, device node, illumination conditions, and process implications

Critical dimension uniformity (CDU) has both across field and across wafer components. CD error generated by across wafer etching non-uniformity and other process variations can have a significant impact on CDU. To correct these across wafer systematic variations, compensation by exposure dose and/or post exposure bake (PEB) temperature have been proposed. These compensation strategies often focus on a specific structure without evaluating how process compensation impacts the CDU of all structures to be printed in a given design. In one previous study limited to a single resist and minimal coater/developer and scanner variations, the authors evaluated the relative merits of across wafer dose and PEB temperature compensation on the process induced CD bias and CDU. For the process studied, it was found that using PEB temperature to control CD across wafer was preferable to using dose compensation. In another previous study, the impact of resist design was explored to understand how resist design, as well as coater/developer and scanner processing, impact process induced bias (PIB). The previous PIB studies were limited to a single illumination case and explore the effect of PIB on only L/S structures. It is the goal of this work to understand additionally how illumination design and mask design, as well as resist design and coater/developer and scanner processing, impact process induced bias (PIB)/OPC integrity.