Tsuyoshi Tamaru

A novel copper interconnection technology using self aligned metal capping method

A self aligned metal capping process for Copper damascene interconnect is newly developed in this study. A tungsten capping layer is selectively formed on the Cu interconnect using the preferential deposition phenomenon of W-CVD assisted by pre and post treatment. This technology is applied to 0.2 /spl mu/m bipolar-CMOS LSI with multilevel Cu interconnects, and then yield, reliability and operation speed are evaluated.

Process and reliability of air-gap Cu interconnect using 90-nm node technology

A self-aligned air-gap interconnect process was proposed. The key features include: 1) a simple process using a conventional Cu damascene process; 2) the combination of a sacrificial layer and a dry-etching process that do not cause any damage to Cu wires; 3) a self-aligned, maskless structure for gap formation; and 4) the preservation of mechanical integrity. In this paper, the air-gap Cu metallization was applied to 130- and 90-nm node CMOS. Four levels of Cu/air-gap interconnects were successfully fabricated and the reliability of the technology was investigated. There were distinct improvements of the leakage current and the time-dependent dielectric breakdown characteristic by the application of an air-gap. Moreover, the air-gap interconnect was further improved with a selective W sealing process. This results in a drastic reduction of the capacitance and the effective dielectric constant.

Simple self-aligned air-gap interconnect process with Cu/FSG structure

A novel self-aligned air-gap interconnect process with Cu/FSG structure was proposed. The key feature is the use of an easily removal sacrifice film by dry-etching process with a reducing gas. This process consists of a conventional Cu damascene process with 130 nm node CMOS technology. In this study, a 2 level Cu interconnect was fabricated and the effective dielectric constant of 2.3/spl sim/2.6 has been successfully achieved. These are consistent with the capacitance reduction by 37/spl sim/41% compared with a conventional Cu/FSG structure.

Impact of Cu barrier dielectrics upon stress-induced voiding of dual-damascene copper interconnects

In this paper, we discuss the stress-induced voiding (SIV) in dual-damascene Cu interconnects. To relax the Cu stress and its gradient, we focused on the Cu barrier dielectrics. The SIV of Cu interconnects was successfully suppressed by using SiC film as a Cu barrier dielectric. The finite element method (FEM) and the molecular dynamics (MD) analysis revealed the stress distribution and its effects on the void growth.

Reliability improvement in blanket tungsten CVD contact filling process for high aspect ratio contact

The reliability improvement of submicron contacts filled by a blanket tungsten process is studied. It is found that, for contacts with an aspect ratio around 2.0, the contact resistance is initially high and increases drastically with additional heat treatment, finally resulting in open failure. This failure mode is caused by chemical reaction on the interface through a previously deposited, porous, glue layer of sputtered tungsten during high-pressure blanket tungsten CVD processing. This reaction occurs at the bottom corner of the contact. A few minutes of hydrogen annealing, followed by a low-pressure hydrogen reduction CVD tungsten nucleation step, suppresses the failure mode drastically. A mechanism for this process in which hydrogen annealing induces selective growth of CVD tungsten only around weak spots in the sputtered tungsten film, thus suppressing WF/sub 6/ intrusion, is proposed.<<ETX>>