Junji Noguchi

Dominant factors in TDDB degradation of Cu interconnects

The field acceleration factor (/spl gamma/) for the E-model of time-dependent dielectric breakdown (TDDB) in various Cu interconnect structures has been studied. The /spl gamma/ for pSiCN structures is larger than that of pSiN structures and independent of the kind of interlayer dielectric material or other processes used to make it. The relationship between the breakdown electric field strength (E/sub BD/) and the TDDB lifetime has been investigated. It has been demonstrated that the TDDB lifetime can be predicted from experimentally measured E/sub BD/ and /spl gamma/. An E/sub BD/ of at least 4.2 MV/cm is necessary to assure ten-year reliability under 0.2 MV/cm operation. Moreover, the important factors influencing the TDDB lifetime for Cu interconnects have been discussed. These include the Cu chemical-mechanical polishing (CMP), the post-CMP annealing, line edge roughness, and fine line effect.

Impact of low-k dielectrics and barrier metals on TDDB lifetime of Cu interconnects

Time-dependent dielectric breakdown (TDDB) in Cu metallization and the dependence on the presence of barrier metal, barrier metal thickness, the kind of barrier metals and the low-k dielectrics, is investigated. There is a distinct difference in TDDB degradation mechanism with and without barrier metals. TDDB degradation of Cu interconnects without and with barrier metal is caused by bulk mode and CMP-surface mode, respectively. The TDDB characteristics with barrier metal are almost the same for different barrier metal thicknesses and depends much more strongly on the electric field strength than the MIS structure. Additionally, both degradations, related to Cu-ion diffusion, are mainly caused not by thermal stress but by electrical stress. The barrier properties of Ta and TaN are better than those of TiN against Cu-ion diffusion into dielectrics, for TDDB. In the case of a low-k structure, TDDB properties with barrier metal also depend on the CMP-surface. With low-k dielectrics, the electric field strength is concentrated near the CMP surface and the TDDB lifetime reduces as the k-value decreases. However, all low-k structures in this study are able to satisfy the 10-year TDDB reliability specifications for the capacitor.

Suppression of stress-induced voiding in copper interconnects

Studied stress-induced voiding in Cu interconnects in the temperature range below 250/spl deg/C, and found two different voiding modes. One mode occurs inside a via having wide wire above it, and can be suppressed by optimizing the via shape and the via-cleaning process. The other mode occurs under a via having wide wire below it and can be suppressed by increasing the Cu grain size and improving the adhesion of the barrier metal with Cu.

Control of Photocorrosion in the Copper Damascene Process

Since chemical mechanical polishing for damascene processes producing copper interconnections is a wet-chemical treatment, corrosion control is indispensable. In addition to ordinary corrosion due to chemical and galvanic reactions with slurries, a new type of corrosion, pattern-specific corrosion, was found. It was clarified to be a kind of anodic corrosion observed only when the damascene process was used to make copper interconnections for active devices, occurring after the metal polishing is completed and the electrodes are electrically separated from each other. A positive potential is generated on the copper electrodes connected to the p + -diffused region against that connected to the n + -diffused region of a p-n junction when the fabrication is carried out in a light environment. The positively biased electrodes corrode quickly, especially in diluted rather than undiluted slurries, resulting in pattern-specific photocorrosion. Less corrosive slurries, especially in diluted state, or corrosion-preventing cleaning methods are therefore needed.

Effect of NH/sub 3/-plasma treatment and CMP modification on TDDB improvement in Cu metallization

Time-dependent dielectric breakdown (TDDB) between Cu interconnects is investigated. TDDB lifetime strongly depends on the surface condition of the Cu interconnect and surrounding pTEOS. A NH/sub 3/-plasma treatment prior to cap-pSiN deposition on Cu interconnect improved the dielectric breakdown lifetime (T/sub BD/) over cap-pSiN deposition only. The plasma treatment also has the beneficial effect of suppressing wiring resistance increase during pSiN deposition. These results suggest that CuO reduction to Cu, and CuN formation at the Cu interconnect surface prevents Cu silicidation during pSiN deposition. Furthermore, SiN formation and bond termination by hydrogen radicals at the pTEOS surface diminish surface defects such as dangling bonds. TDDB lifetime also strongly depends on the Cu CMP process, in which mechanical damage of the SiO/sub 2/ surface during CMP process degrades TDDB. Adoption of a mechanical damage free slurry or a post-CMP HF treatment to remove the damaged layer from the surface improves TDDB.

A novel copper interconnection technology using self aligned metal capping method

A self aligned metal capping process for Copper damascene interconnect is newly developed in this study. A tungsten capping layer is selectively formed on the Cu interconnect using the preferential deposition phenomenon of W-CVD assisted by pre and post treatment. This technology is applied to 0.2 /spl mu/m bipolar-CMOS LSI with multilevel Cu interconnects, and then yield, reliability and operation speed are evaluated.

TDDB improvement in Cu metallization under bias stress

Time-dependent dielectric breakdown (TDDB) between Cu interconnects is investigated. TDDB lifetime strongly depends on the surface condition of the Cu interconnect and surrounding pTEOS. A NH/sub 3/-plamsa treatment prior to cap-pSiN deposition on Cu interconnect improved the dielectric breakdown lifetime (/spl tau//sub BD/) over cap-pSiN deposition only. The plasma treatment also has the beneficial effect of suppressing wiring resistance increase during pSiN deposition. These results suggest that CuO reduction to Cu, and CuN formation at the Cu interconnect surface prevents Cu silicidation during pSiN deposition. Furthermore, SiN formation and bond termination by hydrogen radicals at the pTEOS surface diminish surface defects, such as dangling bonds. TDDB lifetime also strongly depends on the Cu CMP process, in which mechanical damage of the SiO/sub 2/ surface during CMP process degrades TDDB. Adoption of a mechanical damage free slurry or a post-CMP HF treatment to remove the damaged layer from the surface improves TDDB.

Influence of post-CMP cleaning on Cu interconnects and TDDB reliability

The etching amount of Cu wires produced by post-chemical-mechanical polishing cleaning was studied. By using polyvinyl alcohol brush cleaning, the cleaning strength concentrates on the center chip of the wafer, which leads to the erosion of Cu interconnects. The etching depths of isolated Cu wires and dense Cu wires were compared. The surface on the isolated Cu wires is etched deeply because of the nonliner diffusion of the solution and the difference between the friction strengths of both wire patterns. These etching depths were improved by optimizing the brush formation, the rotation speed of the roller and the brush, and by using organic-acids. With respect to the dependence of time-dependent dielectric breakdown (TDDB) lifetime on waiting time, there is a difference between the diluted hydrofluoric-acid (DHF) and organic-acid solutions. The TDDB lifetime for the DHF cleaning is similar until after a waiting time of ten days, whereas the TDDB lifetimes for organic-acids are similar until after a waiting time of four days.

Process and reliability of air-gap Cu interconnect using 90-nm node technology

A self-aligned air-gap interconnect process was proposed. The key features include: 1) a simple process using a conventional Cu damascene process; 2) the combination of a sacrificial layer and a dry-etching process that do not cause any damage to Cu wires; 3) a self-aligned, maskless structure for gap formation; and 4) the preservation of mechanical integrity. In this paper, the air-gap Cu metallization was applied to 130- and 90-nm node CMOS. Four levels of Cu/air-gap interconnects were successfully fabricated and the reliability of the technology was investigated. There were distinct improvements of the leakage current and the time-dependent dielectric breakdown characteristic by the application of an air-gap. Moreover, the air-gap interconnect was further improved with a selective W sealing process. This results in a drastic reduction of the capacitance and the effective dielectric constant.

High-Performance p-Channel LDMOS Transistors and Wide-Range Voltage Platform Technology Using Novel p-Channel Structure

High-performance p-channel lateral double-diffused MOS (LDMOS) transistors designed to operate in a wide voltage range from 35 to 200 V and built using silicon-on-insulator LDMOS platform technology were studied. A novel channel structure was applied, and consequently, a high saturation drain current of 172 μA/μm in the 200-V p-channel LDMOS transistor was achieved, which is comparable to that of an n-channel LDMOS transistor. A low on -resistance of 3470 mΩ·mm2 was obtained while maintaining high on- and off-state breakdown voltages of -240 and -284 V. The 35-200-V LDMOS transistors with low on-resistance were also demonstrated by optimizing the layout, i.e., the reduced surface field structure and field plates.