Alberto García Ortiz

Prototyping of a high performance generic Viterbi decoder

For its proven efficiency, the Viterbi algorithm is widely used for decoding convolutionally encoded messages. In this work, a high performance generic soft input hard output Viterbi decoder is presented and prototyped on an FPGA board. The presented Viterbi decoder is intended to be used in a complete wireless LAN transceiver prototype. The genericity of the design facilitates not only the prototyping of Viterbi decoders with different specifications, but moreover it facilitates the exploration the performance of different implementations in order to obtain the most suitable solution for a particular communication system.

Adaptive coding in networks-on-chip: transition activity reduction versus power overhead of the codec circuitry

This work investigates the reduction of power consumption in Networks-on-Chip (NoCs) through the reduction of transition activity using data coding schemes. The estimation of the NoC power consumption is performed with basis on macromodels which reproduce the power consumption on each internal NoC module according to the transition activity on its input ports. Such macromodels are embedded in a system model and a series of simulations are performed, aiming to analyze the trade-off between the power savings due to coding schemes versus the power consumption overhead due to the encoding and decoding modules.

Power estimation based on transition activity analysis with an architecture precise rapid prototyping system

In this paper a technique is proposed to gather statistical data concerning transition activity of the interface signals in a complex application. By using an architecture precise rapid prototyping system, the signals can be analyzed over a long period of time and therefore a realistic estimation of the signal activity characteristics can be obtained. This information can be used for estimating the power consumption in the final system as well as for a later refinement of the communication structures and single processing blocks. Because of the huge amount of data that would be generated by a real time monitoring, a statistical compression module was implemented. This module allows the trade off between hardware efficiency and accuracy in order to offer a flexible use in prototyping systems. The proposed approach has been validated in a baseband implementation of a simplified OFDM transmitter.

Power consumption in point-to-point interconnect architectures

As technology shrinks, the importance of the communication architecture in the overall system performance and power consumption increases dramatically. In this work, a framework is developed to estimate the consumption in point-to-point interconnect structures under different anti-crosstalk techniques and bus encoding schemes. To model the effect of cross coupled capacitances, the spatial correlation between adjacent bus lines is considered. Assuming that the data has a Gaussian distribution, both temporal and spatial transition activities are estimated from the signal world level statistics using a polynomial function of the activity in the most significant bit. Analog simulations have been carried out to show the accuracy of the proposed model.

Evaluating the impact of data encoding techniques on the power consumption in networks-on-chip

This work addresses the problem of power consumption in networks-on-chip (NoCs). It investigates the reduction of dynamic power consumption through the reduction of transition activity using data coding techniques. Power macromodels for various NoC modules were built, allowing the estimation of the power consumption as a function of the transition activity at each modules inputs. Such macromodels were embedded in a system model and a series of simulations were performed, aiming to analyze the trade-off between the power savings due to coding techniques versus the power consumption overhead due to the encoding and decoding modules.

A linear model for high-level delay estimation in VDSM on-chip interconnects

This work introduces a linear model for high-level prediction of delay in capacitively and inductively coupled very deep sub-micron (VDSM) on-chip interconnects. The proposed estimation model approximates the signal delay as a linear combination of the contributions induced by each other aggressor line. It accurately predicts the delay in both capacitively and inductively coupled lines for the complete set of the switching patterns, and not only for the worst case, as in previous works. Therefore, it is suitable for fast yet efficient high-level analysis of bus encoding schemes envisaging delay minimisation. The accuracy of the model has been assessed by means of extensive experiments using 3D field solvers and SPICE simulations.

Analysis of bandpass sigma-delta modulator architectures

This work analyses two architectures of bandpass sigma delta modulators, in order to find their sensitivity against operational amplifier finite voltage gain, having in mind a switched capacitor realization of both architectures. Expressions for the ideal signal to noise ratio and dynamic range of both architectures are found, as well as a model of the degradation of the mentioned parameters due to finite values of the voltage gain. The proposed model is then compared with nonlinear high level simulations including the effect of finite voltage gain.

A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects

This work introduces an extended linear pattern-dependent model for high-level signal delay estimation in high-speed very deep sub-micron point-to-point interconnects. The proposed model accurately predicts the delay in both inductively and capacitively coupled lines for the complete set of the switching patterns and not only for capacitively coupled lines or worst-case delay as in previous works. We also consider process variations in the formulation of the model and propose a moment-based approach for the inclusion of variations. The accuracy of the model has been assessed by means of extensive experiments. Moreover, we show how the model can be applied at high levels of abstraction in order to explore coding-based alternatives to improve throughput

A constraint length and throughput reconfigurable architecture for Viterbi decoders

The use of dynamically reconfigurable architectures is particularly profitable when utilized in multi-standard systems. In this work, we propose a constraint length and throughput reconfigurable architecture for Viterbi decoders. Based on the Radix-2 single delay feedback architecture, we introduce an extension that can realize both the ACS and the trellis window unit of Viterbi decoders. The presented approach facilitates not only constraint length and throughput reconfigurability, but moreover, tradeoff between power consumption and decode quality. The proposed architecture can be easily reconfigured by adding or removing standard building blocks. Moreover, the techniques introduced here can be easily employed in any DSP application with a butterfly-like data flowgraph and therefore, can benefit the design of DSP coarse grain reconfigurable systems.

Emulation of analog components for the rapid prototyping of wireless baseband systems

The increasing complexity of modern wireless baseband systems demands the use of rapid prototyping methodologies to provide an early estimation of system functionality and performance. In order to achieve an efficient hardware emulation, the complete system including the analog part should be prototyped. In this work we present synthesizable descriptions of a communication channel module and a sigma delta modulator, suitable for fundamental emulation of wireless baseband environments. By avoiding time-intensive hardware/software cosimulation, a great speedup of the system verification can be attained. In order to assist the designer and speed up the design process we also created an environment for automatically customizing the modules according to a specific scenario.