Tuhin Guha Neogi

On the Performance of Lateral SiGe Heterojunction Bipolar Transistors With Partially Depleted Base

This paper discusses improvements to a lateral bipolar device capable of integration into the existing CMOS process flow. With the help of simulations, we demonstrate that the emitter transit time limits the cutoff frequency of a lateral bipolar device. We show that with the introduction of a heterojunction and a partially depleted base, we can decrease the emitter transit time and increase the current gain and the cutoff frequency (ft) of the device. For a balanced design, our simulations indicate an n-p-n device with an ft of 812 GHz and an fmax of 1.08 THz; and a p-n-p device with an ft of 635 GHz and an fmax of 1.15 THz. The collector current at cutoff frequency for both n-p-n and p-n-p devices is ~0.03 mA-roughly 100 times lower than commercial vertical heterojunction bipolar transistors.

Design space analysis of novel interconnect constructs for 22nm FDX technology

In this paper, we describe an integrated design space analysis approach consisting of full factorial layout generation, lithography simulations with added proximity effects, and rigorous statistical analysis through monte-carlo simulations which is used in the evaluating interconnects. This agile Design rule development process provides a quick turnaround time to down-select the potential layout configurations that can offer a competitive, robust and reliable design and manufacturing. Further layout and placement optimization is carried out to evaluate intra-cell, inter-cell and cell boundary situations, which are critical for a place and routed block. These interconnects developed using the integrated approach has been the key contributor to give 20-30% higher performance at the same Iddq leakage for 8T libraries compared to Single Diffusion break or Double Diffusion break based 12T libraries in 22FDX Technology.

140 Gb/s Serializer Using Clock Doublers in 90 nm SiGe Technology

Many design challenges exist in achieving high frequency clocking for high-speed applications. This paper describes a new clock distribution technique and clocking approach with the use of clock doublers in close proximity to sub-circuits to achieve higher data rates, and in many cases, reduce design complexity and power in serializers. A half-rate 4:1 serializer using this unique frequency doubling clock distribution technique has been implemented in a 90 nm BiCMOS process. The design includes a 210-1 pattern length LFSR with phase shifting logic as the testing circuit and a high bandwidth cascoded output driver. The chip has the dimensions of 1.8 × 2.2 mm 2 and consumes 5.78 W from a -3.4 V supply voltage at 140 Gb/s.

Thermal Modeling of 3-D Stacked DRAM Over SiGe HBT BiCMOS CPU

We have previously evaluated the feasibility of a serial code accelerator core with 3-D DRAM stacked on the core operating at high frequencies. While operating at such high frequencies (>24 GHz), there are concerns with removing heat from the 3-D stack. We propose the use of thin diamond sheets, which have high thermal conductivity, as a heat spreader by bonding it close to the processor core substrate and memory stacks. We show, through thermal modeling using COMSOL finite-element analysis tools, the feasibility of diamond as an effective heat spreader in a processor-memory 3-D stack.