Mark A. Zaleski

Integration of an EUV metal layer: a 20/14nm demo

EUV technology has steadily progressed over the years including the introduction of a pre-production NXE:3100 scanner that has enabled EUV process development to advance one step closer to production. We have carried out the integration with 20/14nm metal layer design rules converting double patterning with ArF immersion process to EUV with a single patterning solution utilizing a NXE3100 exposure tool. The exercise through the integration of a mature test chip with an EUV level has allowed us to have early assessment of the process challenges and new workflow required to enable EUV to the mass production stage. Utilizing the NXE3100 in IMEC, we have developed an OPC model and a lithography process to support 20/14nm node EUV wafer integration of a metal layer in conjunction with immersion ArF. This allows early assessment of mix-and-match overlay for EUV to immersion system that is critical for EUV insertion strategy as well as further understanding of the litho process, OPC, and mask defect control specific to EUV single patterning. Through this work we have demonstrated high wafer yields on a 20nm test vehicle utilizing single EUV Metal layer along with additional ArF immersion levels. We were able to successfully demonstrate low mask defectivity and good via chain and open/short electrical yield. This paper summarize the learning cycles from mask defect mitigation and mix machine overlay through post metal CMP wafer integration highlighting the key accomplishments and future challenges.