Jason Eugene Stephens

Challenges of analog and I/O scaling in 10nm SoC technology and beyond

Continuous process-level and system-level innovation has driven Moores Law scaling for the last fifty years, and will continue to do so in the next decades. In the last two decades, there has been an acceleration of new materials and devices into semiconductor manufacturing, such as low-k, strained Si, high-k, and FinFET, in order to continue process and cost scaling. At the same time, ever increasing component integration on SoCs has further driven cost scaling, allowing the current mobile era to take shape. In the next decade, the focus of SoC innovation will be on patterning and low-resistance materials on the process side, and multi-die package integration on the system side.

Planarity considerations in SADP for advanced BEOL patterning

In this paper, the impact of gap-fill planarity on Multi-Self-Aligned Block, SADP (self-aligned double patterning) process for advanced optical technology nodes (7 nm/5 nm) interconnects was studied through process emulations. This study specifically focuses on the insertion of an etch stop layer (ESL) between two coatings of organic planarization layer (OPL), referred to as the tri-layer PM (pattern mask), which enables a thinner OPL for pattern transfer while adding topography correction for non-mandrel block patterning processes. This scheme reduces pillar aspect ratio for improved CD control and flop-over mitigation, as well as topography correction to mitigation false metal patterns in field regions. However, ESL could cause CD variation if it was deposited on the sidewall of spacer where it is a function of the conformality of ESL deposition.

Segment removal strategy in SAQP for advanced BEOL application

In this paper, a strategy of performing segment removal in an SAQP (self-aligned quadruple patterning) and its implication on interconnect parasitic capacitance are reported. In order to reduce the cost and process complexity, through process emulations, this study specifically focuses on not introducing additional lithography step(s) or material to the conventional SADP (self-aligned double patterning) integration. Four SAQP process integrations are demonstrated to selectively remove dummy lines in between the signal lines from sea of lines, as a result, the line to line capacitance can be reduced. The conventional non-mandrel block lithography step will only remove every other line. Typically, to remove more lines requires an additional hard mask layer and a first non-mandrel block lithography step where the line to line capacitance can be further reduced. However, in this study, a double spacer transfer scheme is proposed to achieve the same final structure but without the additional hard mask layer and lithography step. Therefore, this could be another option for 7 nm or 5 nm process integration of BEOL interconnects.

10nm local interconnect challenge with iso-dense loading and improvement with ALD spacer process

10nm M1 local interconnect is using three-color litho-etch-litho-etch-litho-etch (LELELE) integration to enable technology scaling. This paper discusses the challenges to balance the three-color density in critical standard cell scaling, illustrates the limited process margin resulting from iso-dense loading during dry etch CD shrink, and proposes a novel ALD spacer-shrink process which improves iso-dense CD difference by 50%.