Tuhin Subhra Das

A Novel Routing Algorithm for On-Chip Communication in NoC on Diametrical 2D Mesh Interconnection Architecture

To meet the design productivity, scalability and signal integrity challenges of next-generation system designs, a structured and scalable interconnection architecture, network on chip (NoC), has been proposed recently to solve the complex on-chip communication problem. In an NoC, the communication among different nodes is achieved by routing packets through a pre-designed network fabric according to some architecture rather than wires. In Diametrical 2D Mesh architecture, advantages of routing include smaller network diameter as well as larger bisection width. Again, fast network access requires a well-constructed optimal routing algorithm. Our proposed routing algorithm ensures that the packet will always reach the destination through the shortest path and it is deadlock free.

Network-on-chip routing using Structural Diametrical 2D mesh architecture

Performance of a NoC (network-on-chip) strongly depends on its underlying architecture and related routing techniques. A structural scalable interconnection architecture may significantly increase the performance of a NoC in terms of scalability, modularity, transport latency and parallelism in communication. Well-constructed network architecture will also balance load of the network and try to reduce the chance of causing a hot spot on the network. In this work, our primary objective was to design an efficient NoC architecture to increase its performance in all these aspects with distribution of the load across the network and trying to reduce the diameter of the network in order to reduce the cost of routing. In this paper, we present a new architecture, called Structural Diametrical 2D (SD2D) mesh based on Structural Diametrical XY deterministic routing algorithm that tries to balance the load of the network, increase the level of parallelism, ensures that the packet will always reach the destination through the possible shortest path, and the path is deadlock free.

FL2STAR: A novel topology for on-chip routing in NoC with fault tolerance and deadlock prevention

CMP (Chip Multiprocessor) based architectures have offered a promising solution in tomorrows high performance computing demands. Topology and routing policy are playing key roles in designing such architectures to develop a NoC (Network-on-Chip). Major influencing design metrics include scalability, modularity, transport latency, parallelism, and, efficient load-balancing (to avoid generation of hot spots). Efficiency of topology as well as good routing policy is again counted in terms of its ability of fault tolerance and its deadlock prevention scheme. In this work, our primary objective was to design an efficient scalable NoC architecture with efficient fault tolerant routing policies to improve performance of a NoC from all these aspects. This not only reduces the network latency considerably but also tries to balance the load of the network as well as ensures that the packet will always reach the destination through the possible shortest deadlock free path.

Routing in noc on diametrical 2d mesh architecture

Network-on-Chip (NoC) has proven itself as a viable alternative for the on-chip communication among processing cores in recent years. In Diametrical 2D Mesh architecture, advantages of routing include smaller network diameter as well as larger bisection width. Again, fast network access requires a well-constructed optimal routing algorithm. Our proposed routing algorithm ensures that the packet will always reach the destination through the shortest path and it is deadlock free.

A performance enhancing hybrid locally mesh globally star NoC topology

With the rapid increase in the chip density, Network-on-Chip (NoC) is becoming the prevalent architecture for todays complex chip multi processor (CMP) based systems. One of the major challenges of the NoC is to design an enhanced parallel communication centric scalable architecture for the on chip communication. In this paper, a hybrid Mesh based Star topology has been proposed to provide low latency, high throughput and more evenly distributed traffic throughout the network. Simulation results show that a maximum of 62% latency benefit (for size 8x8), 55% (for size 8x8), and 42% (for size 12x12) throughput benefits can be achieved for proposed topology over mesh with a small area overhead.

SD2D: A Novel Routing Architecture for Network-on-Chip

Properly structural scalable interconnection architecture may significantly increase the performance of a Network-on-Chip (NoC) in terms of scalability, modularity, transport latency and parallelism in communication. Well constructed network architecture can also balance load of the network and try to reduce the chance of causing a hot spot on the network. In this work, our primary objective was to design an efficient NoC architecture to increase its performance in all these aspects with distribution of the load across the network as well as trying to reduce the diameter of the network in order to reduce the cost of routing. In this paper, we present a new architecture, called Structural Diametrical 2D (SD2D) mesh based on Structural Diametrical XY deterministic routing algorithm that tries to balance the load of the network, increase the level of parallelism, ensures that the packet will always reach the destination through the possible shortest as well as deadlock free path.