Shih-Chieh Wu

Flexible Three-Bit-Per-Cell Resistive Switching Memory Using a-IGZO TFTs

This letter proposes a novel high bit density nonvolatile memory using a logic compatible flexible amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) structure fabricated at low temperature. Before electrical forming, the a-IGZO TFT exhibits excellent transistor performance, including an ON/OFF current ratio of 8.8×106, a steep subthreshold slope of 0.14 V/decade, a threshold voltage of 0.55 V, and a maximum field-effect mobility of 2 cm2/Vs. After electrical forming, a three-bit-per-cell resistive switching memory is realized using localized multilevel resistance states at the drain and source bits. Combining dual functionalities to achieve low-cost integration and excellent device characteristics at bending states, the proposed device is promising for future system-on-plastic applications.

Multi-bit-per-Cell a-IGZO TFT resistive-switching memory for system-on-plastic applications

We reported a novel flexible nonvolatile memory using complete logic-compatible a-IGZO TFTs fabricated at room temperature. The memory device utilized localized and independent resistive switching for high-density two-bit-per-cell and multi-bit-per-cell operations. Combining low-temperature fabrication, low-cost integration, high bit-density, and excellent flexible memory characteristics, this device shows promise for future system-on-plastic applications.

Novel Two-Bit-per-Cell Resistive-Switching Memory for Low-Cost Embedded Applications

A novel two-bit-per-cell embedded nonvolatile memory (NVM) device requiring no additional mask and process modification in a logic technology has been proposed using a low-temperature poly-Si thin-film transistor with a gate stack. The feature of two-bit-per-cell is realized by independent localized resistive switching (RS) at the drain and source bits, respectively, and enables increased bit density over the present single-poly NVM for low-cost embedded applications. Furthermore, minimal degradation of the transistor characteristics after RS allows interchangeable logic/memory operations in an identical device.

Characterization of Polycrystalline Silicon Thin-Film Transistors with Nickel-Titanium Oxide Gate Dielectric Coating by Sol-Gel Method

With Nickel-Titanium Oxide Gate Dielectric Coating by Sol-Gel Method Shih-Chieh Wu, Rong-Chia Yen, Chih-Kang Deng, Tien-Sheng Chao, Shiow-Huey Chuang, and Tan-Fu Lei Institute of Electronics, National Chiao-Tung University, Taiwan 2 Institute of Electrophysics, National Chiao-Tung University, Taiwan Department of Applied Chemistry, National University of Kaohsiung, Taiwan Phone: +886-3-5712121 ext 54219; Fax: +886-3-5724361; E-mail: sjwu.ee94g@nctu.edu.tw

High-Performance Polycrystalline Silicon Thin-Film Transistor with Nickel-Titanium Oxide by Sol-Gel Spin-Coating and Fluorine Implantation

A high-performance poly-Si TFTs is reported without additional hydrogenation or advanced phase crystallization techniques. Excellent electrical characteristics are attributed to the promising high-κ NiTiO3 by sol-gel spin-coating and the trap passivation by fluorine implantation. Meanwhile, the hot-carrier reliability is greatly improved by the robust Si-F bonds. Introduction Polycrystalline silicon thin-film transistors (poly-Si TFTs) have attracted much attention because of their various applications, such as driving circuits of the active matrix liquid crystal displays (AM-LCDs) and those of the active matrix organic light emitting diode displays (AM-OLEDs) [1] [2]. Nickel-titanium oxide (NiTiO3) deposited by physical vapor deposition was shown to be a promising high dielectric constant (high-κ) gate dielectric [3]. Recently, we have reported a p-channel poly-Si TFT with the NiTiO3 gate dielectric by sol-gel spin-coating [4]. To further improve the TFT characteristics, defect passivation such as hydrogen plasma treatment is often necessary. However, weak Si-H bonds tend to degrade device reliability. Fluorine implantation was reported to passivate defects by more robust Si-F bonds [5]. In this paper, high performance n-channel poly-Si TFTs is reported by taking advantage of the high-κ NiTiO As shown in Fig. 2, an accumulation capacitance density of 410 nF/cm 3 gate dielectric by sol-gel spin-coating and the fluorine implantation. Device Fabrication and Experimental Procedures The schematic of the poly-Si TFT with TaN metal gate and NiTiO3 gate dielectric is shown in Fig. 1. First, 50-nm amorphous silicon (a-Si) was deposited on 550-nm SiO2 by low-pressure chemical vapor deposition (LPCVD) at 550°C, followed by the fluorine implantation with projected ion range at the middle of a-Si film and dosage of 5 × 10cm. The a-Si layer was subjected to recrystallization at 600°C for 24 h in N2 ambient, and the photolithography patterning of the active region. The N source and drain were done by phosphorus implantation and activation at 600°C for 12 h. Next, NiTiO3 film was spin-coated on a 3-nm SiO2 layer using a NiTiO3 sol-gel solution and then baked at 200°C for 10 min to remove the solvent. The sol-gel solution was synthesized by dissolving nickel acetate tetrahydrate [Ni(OOCCH3)2.4H2O] and titanium isopropoxide [Ti(OPr)4] in 2-methoxyethanol. The NiTiO3 spin-coating process was repeated for 3 times to obtain a film thickness of about 50 nm. After thermal treatment at 400°C in O2 ambient for 20 min, the samples were subjected to additional rapid thermal annealing (RTA) at 500°C for 30 s in N2 ambient. The gate was defined by TaN deposition and lift-off process. Then, a 400 nm SiO2 passivation layer was deposited by plasma-enhanced chemical vapor deposition (PECVD). To open the contact holes, SiO2 and NiTiO3 were etched by buffered oxide etch (BOE) and HF:H2O = 50:1, respectively. Finally, aluminum pads were defined. The poly-Si TFT with NiTiO3 gate dielectric but without fluorine implantation was also fabricated using the same process flow for comparison. Results and Discussion 2 is achieved for the NiTiO3 film from capacitance-voltage (C-V) measurement, corresponding to the equivalent-oxide thickness (EOT) of 8.4 nm and the effective dielectric constant value of 23.2. Figure 3 shows the transfer characteristics of the poly-Si TFTs with and without fluorine implantation at VDS = 0.1 V and 1 V, respectively. The electrical characteristics of the fluorine-implanted TFT were significantly improved compared to the one without. The threshold voltage (VTH) and the subthreshold swing were decreased from 1.49 to 1.09 V and from 262 to 207 mV/dec., respectively. In addition, the field-effect mobility was increased from 47.5 to 56.7 cm/V-s. The output characteristics of the TFTs with and without the fluorine implantation are shown in Fig. 4. The driving current of the fluorine-implanted TFT had about 60 % improvement at VGS-VTH = 4 V, compared to that without fluorine implantation. The improvements of the electrical performance could be attributed to the passivation of interface states at the gate dielectric/poly-Si interface and trap states in the poly-Si film by the incorporation of fluorine [5]. In order to verify the effect of fluorine passivation, the effective trap-state density (Ntrap) at grain boundaries was calculated from the grain-boundary trapping model proposed by Levinson et al. [6]. Figure 5 depicts the ln[(IDS/(VGS − VFB)] versus 1/(VGS − VFB) at VDS = 0.1 V. The extracted Ntrap were 3.8 × 10 cm and 6.6 × 10 cm for the TFTs with and without fluorine implantation, respectively. This result indicated that the incorporation of fluorine can effectively passivate the trap states at grain boundaries. Additionally, hot-carrier stress was carried out by VDS = VGS = 4V to investigate the instability of TFTs. The VTH shift due to the broken Si-Si and Si-H bonds at the gate dielectric/ poly-Si interface during hot-carrier stress is shown in Fig. 6. The TFT with fluorine implantation has better immunity against the hot-carrier stress owing to stronger Si–F bond compared with weaker Si–H and Si–Si bonds in the poly-Si channel region. Finally, the key parameters were summarized in Table I. Conclusion High-performance poly-Si TFTs with high-κ NiTiO3 gate dielectric by sol-gel spin-coating and fluorine implantation have been demonstrated. The superior dielectric properties of high-κ NiTiO3 lead to high gate capacitance density. Both the DC electrical characteristics and hot-carrier reliability are significantly improved by the fluorine implantation and NiTiO3 gate dielectric, suggesting its promise for high-speed and low-power display driving circuits. -479Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials, Tokyo, 2010, pp479-480 P-9-7

Fast visible-light phototransistor using CVD-synthesized large-area bilayer WSe 2

P-channel transition metal dichalcogenide ultrathin-body phototransistor (UTB-PT) with a response time as fast as 100 μs has been demonstrated for the first time using the CVD-synthesized large-area bilayer WSe2. Because of its excellent compatibility with mass production, the application of WSe2 UTB-PT for high-speed proximity interactive display has been proposed.

Logic/resistive-switching hybrid transistor for two-bit-per-cell storage

Various bias schemes in the RS-TFT have been comprehensively investigated. As shown in Table I, the VD-biased bipolar RS is superior for the logic/RS hybrid operation with the ability of two-bit-per-cell storage because of its large program margin, localized filament location, negligible VTH shift, and suppressed gate leakage current. In comparison with other embedded memory technologies, the proposed RS-TFT in this work not only is compatible with logic CMOS technology, but also provides comparable memory performance with a very competitive cell size.

Improvement of polycrystalline silicon thin-film transistors with nickel-titanium oxide by sol-gel spin-coating and nitrogen implantation

Polycrystalline silicon thin-film transistors (poly-Si TFTs) have attracted much attention because of the different applications, such as driving circuits of the active matrix liquid crystal displays (AM-LCDs) and those of the active matrix organic light emitting diode displays (AM-OLEDs) [1, 2]. Nickel-titanium oxide (NiTiO3) deposited by physical vapor deposition was introduced to be a high dielectric constant material [3]. It has been reported that NiTiO3 could be the gate dielectric of poly-Si TFTs by sol-gel spin-coating previously [4]. However, to improve the electrical performance and reliability of poly-Si TFTs, defect passivation such as hydrogen plasma treatment to create Si-H bonds is usually needed. Unfortunately, the weak Si-H bonds tend to degrade device reliability under long-term electrical operation. In this paper, high performance N-type poly-Si TFTs is demonstrated by taking advantage of the high-κ NiTiO3 gate dielectric by sol-gel spin-coating and nitrogen ion implantation technique.