Yao-Jen Lee

3D 65nm CMOS with 320°C microwave dopant activation

For the first time, CMOS TFTs of 65nm channel length have been demonstrated by using a novel microwave dopant activation technique. A low temperature microwave anneal is demonstrated and discussed in this study. We have successfully activated the poly-Si gate electrode and source/drain junctions, BF2 for p-MOS TFTs and P31 for n-MOS TFTs at a low temperature of 320°C without diffusion. The technology is promising for high performance and low cost upper layer nanometer-scale transistors as required by low temperature 3D-ICs fabrication.

High-voltage and high-temperature applications of DTMOS with reverse Schottky barrier on substrate contacts

In this letter, for the first time, application of dynamic threshold voltage MOSFET (DTMOS) with reverse Schottky barrier on substrate contacts (RSBSCs) for high voltage and high temperature is presented. By this RSBSC, DTMOS can be operated at high voltage (>0.7 V), and exhibits excellent performance at high temperature in terms of ideal subthreshold slope, low threshold voltage and high driving current.

Homogeneous barrier modulation of TaOx/TiO2 bilayers for ultra-high endurance three-dimensional storage-class memory.

Three-dimensional vertical resistive-switching random access memory (VRRAM) is the most anticipated candidate for fulfilling the strict requirements of the disruptive storage-class memory technology, including low bit cost, fast access time, low-power nonvolatile storage,and excellent endurance. However, an essential self-selecting resistive-switching cell that satisfies these requirements has yet to be developed. In this study, we developed a TaOx/TiO2 double-layer V-RRAM containing numerous highly desired features, including: (1) a self-rectifying ratio of up to 10³ with a sub-μA operating current, (2) little cycle-to-cycle and layer-to-layer variation, (3) a steep vertical sidewall profile for high-density integration, (4) forming-free and self-compliance characteristics for a simple peripheral circuit design, and (5) an extrapolated endurance of over 10¹⁵ cycles at 100 °C. Furthermore, the switching and self-rectifying mechanisms were successfully modeled using oxygen ion migration and homogeneous barrier modulation. We also suggest the new possibility of monolithically integrating working and storage memory by exploiting a unique tradeoff between retention time and endurance.

Low-Temperature Microwave Annealing Processes for Future IC Fabrication—A Review

Microwave annealing (MWA) and rapid thermal annealing (RTA) of dopants in implanted Si are compared in their abilities to produce very shallow and highly activated junctions. First, arsenic (As), phosphorus (P), and BF2 implants in Si substrate were annealed by MWA at temperatures below 550 °C. Next, enhancing the substitutional carbon concentration ([C]sub) by cluster carbon implantation in (100) Si substrates with MWA or RTA techniques was investigated. Annealing temperatures and time effects were studied. Different formation mechanisms of SiCx layer were observed. In addition, substrate temperature is an important factor for dopant activation during MWA and in situ doped a-Si on oxide/Si substrate or glass were compared to elucidate the substrate temperature effect. After the discussion of dopant activation in Si substrates, low temperature formation of ultrathin NiGe layer is presented. Ultrathin NiGe films with low sheet resistance have been demonstrated with a novel two-step MWA process. In the two-step MWA process, the first step anneals the sample with low power MWA, and the second step applies higher power MWA for reducing sheet resistance. During fixed-frequency microwave heating, standing wave patterns may be present in the MWA chamber resulting in nodes and antinodes and thermal variations over the process wafer. Therefore, the effects of Si or quartz susceptor wafers on dopant activation and sheet resistance uniformity during fixed-frequency MWA were investigated.

Dopant Activation in Single-Crystalline Germanium by Low-Temperature Microwave Annealing

Phosphorus activated in germanium epitaxy atop Si wafer by low-temperature microwave annealing technique was investigated in this letter. Compared to the conventional RTA process, the temperature of phosphorus activation could be 120°C to 140°C which is an improvement in temperature reduction at the same sheet resistance. According to the SRP, up to 150°C reduction in maximum temperature at the same activation concentration (about 2 × 1019 cm-3) could be achieved. Through adjusting the microwave power and process time, sheet resistance could be decreased while suppressing dopant diffusion. In addition, the inserted susceptor wafers above and below the processing wafer also suppressed the dopant diffusion and improved film roughness.

A Low-Temperature Microwave Anneal Process for Boron-Doped Ultrathin Ge Epilayer on Si Substrate

High source/drain concentration level, ultrashallow junction, and high-mobility channel are important for the requirements of nanoscale transistors. Microwave processing of semiconductors could offer distinct advantages over conventional RTP systems in some applications, and the anneal temperature is within the range of 300degC-500degC. By using a low-temperature microwave anneal, the sheet resistance and boron diffusion in the Si/Ge/Si substrate could be reduced effectively, and the crystalline structure of Si/Ge/Si is not damaged according to the TEM image and the XRD signals.

Amorphous-Layer Regrowth and Activation of P and As Implanted Si by Low-Temperature Microwave Annealing

Microwave annealing of dopants in Si has been re ported to produce highly activated junctions at temperatures far below those needed for comparable results using conventional thermal processes. However, the details of the kinetics and mechanisms for microwave annealing are far from well understood. In this paper, 20-keV arsenic (As) and 15-keV phosphorus (P) implants, in a dose range from 1 to 5 × 1015 ion/cm2, were annealed by microwave methods at temperatures below 500°C. These junctions were characterized by profile studies with secondary ion mass spectrometry and spreading resistance profiling, sheet resistance with four-point probe, and extensive use of cross sectional transmission electron microscopy to follow the regrowth of the as-implanted amorphous layers created by the implantation. The amorphous-layer regrowth was observed to be uneven in time, with relatively little amorphous/crystalline interface motion for less than 50 s, followed by rapid regrowth for longer times. Sheet resistance values continued to drop for anneal times after the regrowth process was complete, with some evidence of dopant deactivation for anneal times of 600 s.

Trap-state density in continuous-wave laser-crystallized single-grainlike silicon transistors

This investigation characterizes electrical characteristics of continuous-wave green laser-annealed single-grainlike silicon thin-film transistors in relation to trap-state densities. As laser power increases, highly crystalline channels form, reducing tail-state densities to as low as 3×1019eV−1cm−3. This occurrence is responsible for high field-effect electron mobility of 284cm2∕Vs. In contrast, increasing laser power initially reduces the deep-state density and then increases it to 3×1016eV−1cm−3. This reversal in deep-state density and thus in the subthreshold slope as well as a saturating reduction in threshold voltage are associated with the formation of extra interface defects caused by laser-crystallization-enhanced surface roughness.

Record-high 121/62 μA/μm on-currents 3D stacked epi-like Si FETs with and without metal back gate

A sequential layered integration technology that can fabricate 3D stackable epi-like Si FETs with and without metal back gate (MBG) under sub-400°C are proposed in this article. With laser crystallized epi-like Si and CMP thinning processes for channel fabrication, 3D stackable ultra thin body (UTB) n/p-MOSFETs with low-subthreshold swings (88 and 121 mV/dec.) and high on-currents (121 and 62 μA/μm) are demonstrated. With additional metal back gate structure, UTB devices can be desirably operated in a positive or negative threshold voltage range with γ values of 0.51 (n-MOSFETs) and 0.56 (p-MOSFETs) for favoring its applications in 3D logic circuits. In addition, such thin and high quality channel and metal back gate scheme is not only promising for conventional p-n junction device but also junctionless (JL) scheme, which can simplify the fabrication and achieve further scaling.

High-Performance Schottky Contact Quantum-Well Germanium Channel pMOSFET With Low Thermal Budget Process

We present a high-performance Si/Ge/Si p-channel metal-oxide-semiconductor field-effect transistor (pMOSFET) with a NiSiGe Schottky junction source/drain (S/D) formed through microwave-activated annealing. A Schottky contact S/D is preferable, because the lower process temperature is beneficial for eliminating Ge diffusion. The fabricated NiSiGe Schottky junction exhibited a high effective barrier height (ΦBn) of 0.69 eV for electrons, resulting in a high junction current ratio of more than 105 at the applied voltage of |Va| = 1 V. Our quantum-well pMOSFET exhibited a high ION/IOFF ratio of ~107 (IS) and a moderate subthreshold swing of 166 mV/decade.