Ling-Yen Yeh

2.0 μm electroluminescence from Si/Si0.2Ge0.8 type II heterojunctions

A metal-oxide-semiconductor tunneling diode is used to emit electroluminescence from a Si/Si0.2Ge0.8 heterojunction. Besides the 1.1 μm and 1.6 μm infrared emission from the band edges of Si and SiGe, respectively, 2 μm infrared emission is also observed due to the radiative recombination between the electrons in the Si conduction band and the holes in the SiGe valence band. This type II recombination can emit photons whose energy is below the SiGe band gap to extend the emission range of Si/Ge-based light-emitting devices. The emission line shape can be fitted by the electron-hole-plasma recombination model.

Superior n-MOSFET Performance by Optimal Stress Design

The high-performance n-FET is achieved by ultra- high-stress contact-etch-stop-layer stressor and optimal design of device dimensions. The biaxial-like stress resulting from a high symmetry in device dimension (gate width/gate length ratio is close to one) has the better performance in terms of Ion enhancement, ballistic efficiency, and injection velocity. The multichannel device with a smaller gate width/gate length ratio is proposed to enhance the device performance in the circuit design for the n-FET. The characteristics of the detailed stress simulation and the ballistic-transport measurement reported in this letter suggest that these results remain valid for ballistic-transport devices with 10-20-nm gate length. The stress distribution with different device dimensions was simulated by 3-D finite-element mechanical-stress simulation, and the mobility, ballistic efficiency, and injection velocity were calculated theoretically based on stress characteristics.

Gate width dependence on backscattering characteristics in the nanoscale strained complementary metal-oxide-semiconductor field-effect transistor

It is found that the ballistic efficiency, channel backscattering ratio, and injection velocity, which are the most important parameters for the ballistic transport, are greatly influenced by the stress characteristic in the channel even on the same gate length device. The narrower gate width device provides the best performance for the n-type field-effect transistor (n-FET) with the same gate length. Thus, the multichannel device is proposed to enhance the n-FET performance in the circuit design. The stress distribution with different device structures were simulated by the three-dimensional finite element mechanical stress simulation, and ballistic efficiency and injection velocity were calculated theoretically based on the stress characteristic. The theoretical calculation and the experimental data indicate the causes of the higher ballistic efficiency and injection velocity in narrower gate width devices to be the strain-induced modulation of the carrier mean-free path and smaller electron effective m...

Digital communication using Ge metal-insulator-semiconductor light-emitting diodes and photodetectors

Both Ge light-emitting diodes and photodetectors are demonstrated by using the same metal-insulator-semiconductor (MIS) tunneling structure. A Ge MIS tunneling diode biased at the accumulation region is used as a light-emitting device and a Ge MIS tunneling diode biased at the inversion region is used as a photodetector. The ultrathin gate oxide film used in the MIS tunneling diode was grown by liquid phase deposition at 50 °C to lower the thermal budget. A Ge light-emitting diode has a higher quantum efficiency than a similar Si device (at least one order of magnitude stronger) due to the higher radiative recombination coefficient. With the detection of the Ge MIS photodetector, the data communication in free space is reported and demonstrated for the first time.

Record high current density and low contact resistance in MoS2 FETs by ion doping

Record high current density of 300 μA/μm with low contact resistance of 200 Ω μm and a channel length of 0.8 μm at a drain-source bias of 1.6 V has been achieved for the first time in MoS2 field-effect transistors (FETs) grown by chemical vapor transport. The low contact resistance is achieved using a polyethylene-oxide cesium-perchlorate solid polymer ion conductor formed by drop casting. The charged ions are placed into position over the channel by the application of a bias to a side gate and then locked into place by lowering the temperature. A weak temperature dependence of the drain current after ion doping indicates that transport in the Schottky contacts is dominated by tunneling.

The Dependence of the Performance of Strained NMOSFETs on Channel Width

The dependence of the performance of strained NMOSFETs on channel width was investigated. When the channel width was varied, the stress in the channel varied accordingly. This changed the electron effective mass and, consequently, the on-state current I on. By shrinking the channel width of a strained NMOSFET from 1 to 0.1 mum and by keeping the channel length at 55 nm, the on-state drain current per unit channel width was enhanced by 22%. The gate leakage current was also affected by the stress in the channel, which can be explained by the increase in hole barrier height at the Si/SiO2 interface. Furthermore, when the film stress was increased by 1 GPa, the gate leakage current density Jg of a strained NMOSFET with a channel width of 0.1 mum and a length of 55 nm under a negative bias -3 V was reduced by 63%.

Superior n-MOSFET performance by optimal stress design

In this article we present detailed stress simulation characterization of the 3-D boundary effects and show that the high-performance n FET can be achieved by the ultra-high-stress CESL stressor and optimal geometric structure design. A symmetric structure which results in the biaxial- like stress is favored for n FET in terms of Ion, Bsat rsat, and vnj. The comprehensive study helps the future device circuit design and remains valid for future technology node of 22 nm.

An investigation about the limitation of strained-Si technology

Strained-Si technology is the Holy Grail for present semiconductor industry and is used extensively to boost the device performance, recently. However, the limitation of strained-Si technology has greatly perplexed us and need to investigate in detail. In this work, the low temperature ballistic measurement enables us to discriminate the origin of mobility enhancement under stress from the reduction of effective mass and/or the influence of different scattering mechanisms. It is found that the electron mobility enhancement under stress will become less sensitive when the gate length of device reaches ∼100 nm. The real mechanism of this phenomenon have be proved to the characteristic of device ballistic transport and the optimal stress design developed in this work can further extend the limitation of Strained-Si technology to the smaller gate length region (technology node) (Fig. 1).