Ujjwal Guin

Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain

As the electronic component supply chain grows more complex due to globalization, with parts coming from a diverse set of suppliers, counterfeit electronics have become a major challenge that calls for immediate solutions. Currently, there are a few standards and programs available that address the testing for such counterfeit parts. However, not enough research has yet addressed the detection and avoidance of all counterfeit parts-recycled, remarked, overproduced, cloned, out-of-spec/defective, and forged documentation-currently infiltrating the electronic component supply chain. Even if they work initially, all these parts may have reduced lifetime and pose reliability risks. In this tutorial, we will provide a review of some of the existing counterfeit detection and avoidance methods. We will also discuss the challenges ahead for implementing these methods, as well as the development of new detection and avoidance mechanisms.

Counterfeit Integrated Circuits: Detection, Avoidance, and the Challenges Ahead

The counterfeiting of electronic components has become a major challenge in the 21st century. The electronic component supply chain has been greatly affected by widespread counterfeit incidents. A specialized service of testing, detection, and avoidance must be created to tackle the worldwide outbreak of counterfeit integrated circuits (ICs). So far, there are standards and programs in place for outlining the testing, documenting, and reporting procedures. However, there is not yet enough research addressing the detection and avoidance of such counterfeit parts. In this paper we will present, in detail, all types of counterfeits, the defects present in them, and their detection methods. We will then describe the challenges to implementing these test methods and to their effectiveness. We will present several anti-counterfeit measures to prevent this widespread counterfeiting, and we also consider the effectiveness and limitations of these anti-counterfeiting techniques.

A Comprehensive Framework for Counterfeit Defect Coverage Analysis and Detection Assessment

The increasing threat of counterfeit electronic components has created specialized service of testing, detection, and avoidance of such components. However, various types of counterfeit components – recycled, remarked, overproduced, defective, cloned, forged documentation, and tampered – pose serious threats to supply chain. Over the past few years, standards and programs have been put in place throughout the supply chain that outline testing, documenting, and reporting procedures. However, there is little uniformity in the test results among the various entities. Currently, there are no metrics for evaluating these counterfeit detection methods. In this paper, we have developed a detailed taxonomy of defects present in counterfeit components. Based on this taxonomy, a comprehensive framework has been developed to find an optimum set of detection methods considering test time, test cost, and application risks. We have also performed an assessment of all the detection methods based on the newly introduced metrics – counterfeit defect coverage, under-covered defects, and not-covered defects.

Anti-counterfeit Techniques: From Design to Resign

The emerging threat of counterfeit electronic components has become a major challenge over the past decade. To address this growing concern, a suite of tests for the detection of such parts has been created. However, due to the large test time and cost, it is fairly difficult to implement them. Moreover, the presence of different types of counterfeits in the supply chain - recycled, remarked, overproduced, out-of-spec/defective, cloned, forged documentation, and tampered - makes the detection even more challenging. In this paper, we present a detailed taxonomy of counterfeit types to analyze the vulnerabilities in the electronic component supply chain. We then present the state of knowledge on anti-counterfeit technologies to help prevent counterfeit components from ever entering into the supply chain and to provide capabilities for easy detection.

Low-cost On-Chip Structures for Combating Die and IC Recycling

The recycling of electronic components has become a major concern for the industry and government as it potentially impacts the security and reliability of a wide variety of electronic systems. The sheer number of component types (analog, digital, mixed-signal) and sizes (large or small) makes it extremely challenging to find a one-size-fits-all solution to detect and prevent recycled ICs. In this paper, we propose a suite of solutions for combating die and IC recycling (CDIR). These solutions include light-weight, on-chip structures based on ring oscillators (RO-CDIR), anti-fuses (AF-CDIR) and fuses (F-CDIR). Each structure meets the unique needs and limitations of different part types and sizes providing excellent coverage of recycled parts. HSPICE simulation results using 90nm technology demonstrate the effectiveness of our proposed negative-bias temperature instability (NBTI)-aware RO-CDIR for detecting ICs used for very short period of time. Recycling of large digital ICs can effectively be detected by using AF-CDIR. Small analog and digital recycled components can be identified by testing our F-CDIR with very low cost measurement devices, e.g., a multimeter.

Design of Accurate Low-Cost On-Chip Structures for Protecting Integrated Circuits Against Recycling

The recycling of electronic components has become a major industrial and governmental concern, as it could potentially impact the security and reliability of a wide variety of electronic systems. It is extremely challenging to detect a recycled integrated circuit (IC) that is already used for a very short period of time because the process variations outpace the degradation caused by aging, especially in lower technology nodes. In this paper, we propose a suite of solutions, based on lightweight negative bias temperature instability (NBTI)-aware ring oscillators (ROs), for combating die and IC recycling (CDIR) when ICs are used for a very short duration. The proposed solutions are implemented in the 90-nm technology node. The simulation results demonstrate that our newly proposed NBTI-aware multiple pair RO-based CDIRs can detect ICs used only for a few hours.

FORTIS: A Comprehensive Solution for Establishing Forward Trust for Protecting IPs and ICs

With the advent of globalization in the semiconductor industry, it is necessary to prevent unauthorized usage of third-party IPs (3PIPs), cloning and unwanted modification of 3PIPs, and unauthorized production of ICs. Due to the increasing complexity of ICs, system-on-chip (SoC) designers use various 3PIPs in their design to reduce time-to-market and development costs, which creates a trust issue between the SoC designer and the IP owners. In addition, as the ICs are fabricated around the globe, the SoC designers give fabrication contracts to offshore foundries to manufacture ICs and have little control over the fabrication process, including the total number of chips fabricated. Similarly, the 3PIP owners lack control over the number of fabricated chips and/or the usage of their IPs in an SoC. Existing research only partially addresses the problems of IP piracy and IC overproduction, and to the best of our knowledge, there is no work that considers IP overuse. In this article, we present a comprehensive solution for preventing IP piracy and IC overproduction by assuring forward trust between all entities involved in the SoC design and fabrication process. We propose a novel design flow to prevent IC overproduction and IP overuse. We use an existing logic encryption technique to obfuscate the netlist of an SoC or a 3PIP and propose a modification to enable manufacturing tests before the activation of chips which is absolutely necessary to prevent overproduction. We have used asymmetric and symmetric key encryption, in a fashion similar to Pretty Good Privacy (PGP), to transfer keys from the SoC designer or 3PIP owners to the chips. In addition, we also propose to attach an IP digest (a cryptographic hash of the entire IP) to the header of an IP to prevent modification of the IP by the SoC designers. We have shown that our approach is resistant to various attacks with the cost of minimal area overhead.

Counterfeit Integrated Circuits

Counterfeit integrated circuits (ICs) pose a major concern to the industry and government as they potentially impact the security and reliability of a wide variety of electronic systems. A recent report [1] from the Information Handling Services Inc. [2] shows that reports of counterfeit parts have quadrupled since 2009 (see Fig. 2.1). This data has been compiled from two reporting entities—The Electronic Resellers Association International (ERAI) Inc. [3] and the Government-Industry Data Exchange Program (GIDEP) [4]. This report states that the majority of counterfeit incidents were reported by US-based military bodies and electronic firms from the aerospace industry.

Invasion of the hardware snatchers

In February 2014, the FBI charged a Florida man, Marc Heera, with selling a cloned version of the Hondata s300, a plug-in module for the engine computer that reads data from sensors in Honda cars and automatically adjusts the air-fuel mixture, idle speed, and other factors to improve performance. The plug-in also allows users to monitor the engine via Bluetooth and make their own adjustments. The clones certainly looked like the genuine product, but in fact they contained circuit boards that had likely been built in China, according to designs Heera had obtained through reverse engineering. Honda warned that cars using the counterfeits exhibited a number of problems, including random limits on engine rpm and, occasionally, failure to start. Devices that connect to an engine control unit (ECU) present particular safety concerns; researchers have demonstrated that, through ECU access, they could hijack a cars brakes and steering.

Design for Bit Error Rate estimation of high speed serial links

High speed serial links, consisting of SerDes devices, require the Bit Error Rate (BER) to be at the level of 10−12 or lower. The excessive test time for comparing each captured bit for error detection in the traditional BER measurement and the costly instrumentation are major drawbacks for high volume production test of SerDes devices. In this paper, we propose a design for BER estimation methodology which includes a new BER estimation method, a simple BER test system which incorporates a novel design of time-to-digital converter (TDC).