Ukyo Jeong

Study of reverse annealing behaviors of p+/n ultrashallow junction formed using solid phase epitaxial annealing

Solid phase epitaxial (SPE) annealing at low temperature has the advantage of high dopant activation and very little dopant diffusion. However, due to the low thermal budget engaged in SPE, a large amount of defects can exist in the area beyond the original interface of the crystal and the pre-amorphized layer. These defects may cause severe junction leakage. They may also cause dopant diffusion and deactivation in a following higher temperature process. This work studies the reverse annealing behaviors during a second annealing step for SPE-formed p+/n junction using either 1 keV B+ or 5 keV BF2+ implants. Four-point probe, secondary-ion-mass spectroscopy, and transmission electron microscopy are used in this study. The results show that the boron deactivation after second-step annealing is not only correlated with the transmission electron diffraction (TED), but also correlated with the end of range defect evolution. The results also show that BF2 implanted wafer has slower boron deactivation, less TED ...

Channeling Doping Profiles Studies for Small Incident Angle Implantation into Silicon Wafers

Traditional de‐channeling dopant profiles in the silicon crystal wafers have been achieved by tilting the wafer away from the incident beam. As feature sizes of device shrink, the advantages for channeled doping profiles for implants with small or near zero degree incident angles are being recognized. For example, high‐energy CMOS well spacing limitations caused by shadowing and encroachment of the ion beam by photoresist mask can be avoided for near zero degree incident implants. Accurate models of channeled profiles are essential to predict the device performance. This paper mainly discusses the damage effect on channeled dopant profiles. Especially, damage effects on channeled dopant profiles are correlated to ThermaWave (TW) measurements. It is demonstrated that there is a critical dose at which the damage effects have to be considered for channeled dopant profile evolvements.

Requirements and Challenges in Ion Implanters for Sub‐100nm CMOS Device Fabrication

As CMOS technology moves into sub‐100nm regime, significance of non‐planar structure effects have grown. Traditional ion implant performed at off‐critical angle exhibits shortfalls in device integration and performance merits. Modern ion implanters have evolved to face challenges of on‐axis implants. Ion beam incident angle control is one essential requirement to manage the challenges. This paper describes number of implant applications in modern CMOS fabrication on which required precision in angle control is estimated based on device measurement and TCAD simulations.

Precise beam incidence angle control on the VIISta 810HP

The VIISta 810HP ion implanter has precise control over the angle of incidence of the ion beam to the wafer. The machine is capable of delivering the beam to within ±0.2° of the desired tilt angle. A brief overview of the hardware and software used to achieve this is given in the paper. Experiments have been performed to verify this capability. <100> silicon wafers were implanted at a variety of incidence angles in order to perform a coarse alignment of the wafer platen to the beam using sheet resistance and Thermawave Thermaprobe measurements. Following these implants another series of implants was performed to develop a SIMS calibration curve for implant angle variations in tenths of a degree. The resulting data show both that the calibration technique is viable and that the VIISta 810HP has stable and repeatable control over the beam incidence angle.

Effects of pre-amorphization on junction characteristics and damage behavior in low energy boron implantation

One of the major challenges of meeting the source/drain extension requirements for high performance scaled devices is to achieve low series resistance with shallow junctions. Pre-amorphization has been used to suppress implant channeling and to enhance dopant activation during solid phase crystal re-growth. In this paper the effects of Ge premorphization on the activation of 1 keV boron implants under various thermal treatments have been investigated. The wafers were pre-amorphized with 5 keV 1/spl times/10/sup 15/ cm/sup -2/ Ge/sup +/ implant. Subsequent anneals on some samples were performed in a furnace at temperatures ranging from 500/spl deg/C to 750/spl deg/C for 30 min and some were processed by RTA at 800/spl deg/C to 1050/spl deg/C under various soak times. While the activation behavior above 700/spl deg/C for the crystalline and preaamorphized samples was similar, distinctly different behavior was observed at lower temperatures in the two cases. Lower sheet resistance was obtained In pre-amorphized samples below 300/spl deg/C but reverse annealing is observed when the temperature is increased. Spreading resistance and SIMS analysis were used to generate junction profiles. In addition, TEM analysis was done to understand the physics of the observed phenomenon and to investigate the merits and demerits of preamorphization from a process integration standpoint.

Device Parametric Shift Mechanism Caused by Boron Halo Redistribution Resulting from Dose Rate Dependence of SDE Implant

Change in dopant diffusion was observed for Arsenic source drain extension (SDE) implants when they were performed at various dose rates. The high dose SDE implant amorphizes the surface of the silicon substrate and the thickness of the amorphous layer is strongly influenced by the rate of dopant bombardment. It is well known that the ion implantation process introduces excess interstitials. While the amorphous region is completely re-grown into single crystal during subsequent anneal without leaving behind extended defects, interstitials that are injected beyond the amorphous layer lead to formation of {311} defects or dislocation loops in the end of range region. During thermal processing, these extended defects dissolve, release interstitials, which in turn lead to transient enhanced diffusion of underlying Boron halo dopant. Dopant depth profiles measured by SIMS revealed different amount of Boron pile-up in the near surface region, corresponding to different SDE implant dose rates. In CMOS devices, this surface pile-up would correlate with a Boron pile-up in the channel region that would lead to a shift in transistor characteristics. Through this investigation, we were able to explain the mechanism causing device characteristics shift resulted from SDE implant with the same dose and energy but different dose rates.