Sandeep Mehta

Study of reverse annealing behaviors of p+/n ultrashallow junction formed using solid phase epitaxial annealing

Solid phase epitaxial (SPE) annealing at low temperature has the advantage of high dopant activation and very little dopant diffusion. However, due to the low thermal budget engaged in SPE, a large amount of defects can exist in the area beyond the original interface of the crystal and the pre-amorphized layer. These defects may cause severe junction leakage. They may also cause dopant diffusion and deactivation in a following higher temperature process. This work studies the reverse annealing behaviors during a second annealing step for SPE-formed p+/n junction using either 1 keV B+ or 5 keV BF2+ implants. Four-point probe, secondary-ion-mass spectroscopy, and transmission electron microscopy are used in this study. The results show that the boron deactivation after second-step annealing is not only correlated with the transmission electron diffraction (TED), but also correlated with the end of range defect evolution. The results also show that BF2 implanted wafer has slower boron deactivation, less TED ...

Using Multiple Implant Regions To Reduce Development Wafer Usage

The cost of new process development has risen significantly with larger wafer sizes and the increased number of fabrication steps needed to create advanced devices. The high value of each 300 mm development wafer has spurred efforts to find a way to explore more than a single process setting with each wafer. Traditional methods of defining multiple spatially distinct implant regions on a single wafer achieve poor utilization of device die. The need for efficient utilization of the die and wide process latitude for defining multiple implant regions per wafer has led to the development of an implant proximity mask (vMask™), which permits sharply defined borders between implant regions that may have different species, energy, angle, or dose. The capability of this system to achieve multiple spatially resolved implant conditions per wafer with high die utilization and using the same process parameters as production implants will be described. Specifically, results for measurement of the uniform process area, ...

Onset of Extended Defect Formation and Enhanced Diffusion for Ultra-Low Energy Boron Implants

To meet the challenge of achieving ultra shallow p + /n source/drain extension junctions for 0.1 Oim node devices, ultra low energy boron implant and advanced annealing techniques have been explored. In this paper, we report the extended defect and boron diffusion behavior with various implant and annealing conditions. Boron implants were performed at energies from 0.25keV to lkeV and doses of 5 × 10 14 cm −2 and 1 × 10 15 cm −2 . Subsequent anneals were carried out in nitrogen ambient. The effect of energy, dose and oxide capping on extended defect formation and enhanced dopant diffusion was examined. It was observed that a thin screen oxide layer (35A), grown prior to implantation, reduces the concentration of dopant in the Si by a significant amount as expected. This oxide also reduces the dislocation loops in the lattice and lowers diffusion enhancement of the dopant during annealing. The final junction depth can be optimized by using a low thermal budget spike anneal in a controlled oxygen ambient.

Defect Behavior in BF2 Implants For S/D Applications as a Function of Ion Beam Characteristics

This study investigates characteristics of defects induced by BF2 implantation with 2 different types of ion beams — a spot beam and the other a parallel ribbon beam — on blanket wafers. The effect of dose rate on defect behaviour was also investigated. Transmission Electron Microscopy (TEM) and Ellipsometry measurements were made to understand the damage characteristics. Secondary Ion Mass Spectroscopy (SIMS) analysis was conducted to understand dopant distribution and segregation. In addition, activation of Boron was characterized by sheet resistance measurements. We conclude that it is primarily the inherent difference in dose rate of batch versus single wafer implanters that affects induced defect behaviour in Si.

Channeling Doping Profiles Studies for Small Incident Angle Implantation into Silicon Wafers

Traditional de‐channeling dopant profiles in the silicon crystal wafers have been achieved by tilting the wafer away from the incident beam. As feature sizes of device shrink, the advantages for channeled doping profiles for implants with small or near zero degree incident angles are being recognized. For example, high‐energy CMOS well spacing limitations caused by shadowing and encroachment of the ion beam by photoresist mask can be avoided for near zero degree incident implants. Accurate models of channeled profiles are essential to predict the device performance. This paper mainly discusses the damage effect on channeled dopant profiles. Especially, damage effects on channeled dopant profiles are correlated to ThermaWave (TW) measurements. It is demonstrated that there is a critical dose at which the damage effects have to be considered for channeled dopant profile evolvements.

Effect of Ge Pre-amorphization on Junction Characteristics for Low Energy B Implants

The drive towards developing deep sub-micron CMOS devices places more challenges on semiconductor processing. From the standpoint of doping technology, the challenge is to achieve ultra-shallow p + /n source/drain extension junctions for PMOS. Among the various approaches being pursued to meet this challenge, pre-amorphization was used to curtail channeling of the as-implanted Boron. The effect of pre-amorphization on junction depth and junction sheet resistance in the ultra-low implant energy regime is investigated in this study. Pre-amorphization was achieved with Ge implant. B was implanted at energies of 250eV to 5keV and at a dose of 1×10 15 cm −2 into crystalline and pre-amorphized wafers. Both spike anneal at 1050°C and furnace anneal at 500°C to 750°C were performed after B implants. In all spike anneal cases, the pre-amorphized wafers exhibit higher sheet resistance and shallower junction depth than crystalline wafers. In all furnace anneal cases, shallower junction depth as well as lower sheet resistance can be achieved with pre-amorphized wafers. Higher pre-amorphization energy induces lower sheet resistance after both furnace and rapid thermal anneal (RTA).

Low energy ion implantation and its characterization and processing

Abstract Low energy implants from 20 keV down to 1 keV (with an effective boron energy as low as 225 eV), have been characterized on commercially available implanters. Wafer sizes up to 200 mm have been included. The effects of different modes of operation, such as decel (with various extraction voltages) and drift/extraction mode, on the quality and throughput have been investigated. Both as implanted and annealed SIMS profiles have been obtained. Comparisons are made between RTP and furnace annealing, as well as between various implant measurement techniques such as Therma-Wave and Prometrix. The effects of other processing and physical phenomena will be discussed or presented, i.e., channeling, pre-amorphization, neutrals, point defect formation and enhanced diffusion. Key issues for ultra low energy ion implantation requirements (≤ 2 keV) are discussed.

Process and Equipment Issues in Rapid Thermal Oxidation (RTO)

Thin oxides with thicknesses in the range of 150 to 300A were grown on lOO-mm Si wafers in a commercial RTP reactor. Growth temperatures and times were llO0-1200 ° C for 60-180 seconds in 100% 0 2 at 1 atmosphere. Oxide thickness uniformity was measured using ellipsometry; contour maps of thickness uniformity will be presented. The standard deviation wascalculated to be 2-2.5% within 5 mm of the edge using a method which weights the area represented by each of 45 data points per wafer. In order to correct for dynamic changes in temperature uniformity, a new annealing method was developed.Results on wafer-to-wafer uniformity will be presented. Improvements achieved by post-oxidation annealing in N 2 and electrical uniformity of films will be discussed.

Process Transferability from a Spot Beam to a Ribbon Beam Implanter: CMOS Device Matching

The exercise of dose and energy matching is the standard way to integrate a new implanter into a manufacturing fab. Sheet resistance and secondary‐ion mass spectroscopy (SIMS) measurements on bare silicon wafers have been the conventional metrologies to establish dose/energy equivalence between implanters. Invariably, matched performance on bare silicon wafers translated into matched device performance between implanters of the same kind. However, as devices scale down to 90 run and beyond, the implanter design can become a significant factor in terms of process matching. In this paper we discuss the dynamics of transferring 120–90nm logic processes from a traditional batch, spot beam implanter to a single wafer (SW), parallel ribbon beam implanter. The results show that the traditional approach to dose matching involving the basic parameters of specie, dose and energy, although necessary, is inadequate to provide matched device performance between the two implanter types. 3‐dimensional effects which cann...

APC Implementation on VIISta Ion Implanters

As transistor features shrink, small variations in process steps have a significant impact on device performance and yield. The industry is adopting Advanced Process Control (APC) to control wafer‐to‐wafer variations in several process steps, but to‐date APC has had limited application for implant. For example, lot‐to‐lot adjustments are being used today by chip manufacturers to adjust halo implants. The controls now possible due to the use of single wafer implant systems to adjust for blanket film variations has generated increased interest in implementing APC in the implant bay. Emerging implant APC applications are being implemented using Within wafer (WiW) control and feed‐forward methods to compensate for transistor threshold voltage non‐uniformities introduced during gate etch process steps. In the past, APC applications in implant have lagged other processing steps because of the inability to adjust parameters on batch systems and the lack of on‐board metrology. New in‐situ metrology technologies b...