Naushad Variam

Ultra-low contact resistivity with highly doped Si:P contact for nMOSFET

We report a record setting low NMOS contact Rc of 2e-9 Ωcm2 with an all-silicon based solution. The ultra-low contact resistivity of Ti/Si system of 2e-9 Ωcm2 has been demonstrated with Highly Doped Si:P (HD Si:P) EPI layer which is compatible with FinFET S/D structures combined with millisecond laser anneal activation (DSA). Additionally, we show the pathway to further improve contact resistivity with HD Si:P using P implantation followed by laser anneal to reach the contact resistivity requirement for the 10nm or 7 nm nodes.

Ultra-low NMOS contact resistivity using a novel plasma-based DSS implant and laser anneal for post 7 nm nodes

We report a record-setting low NMOS contact resistivity of 1.2×10^-9 Ωcm² compatible with Ti/Si system and dopant segregation Schottky (DSS) based solution. The ultra-low contact resistivity of Ti/Si system is demonstrated with Highly Doped Si:P Epi layer and P implantation using conformal plasma implant followed by millisecond laser anneal. Additionally, we show that short-pulse nanosecond laser as post implant anneal provides a promising pathway to further improve NMOS ρ_C to below 1×10^-9 Ωcm² for the post 7 nm nodes.

Plasma-assisted low energy N2 implant for Vfb tuning of Ge gate stacks

This work reports Vfb tuning of TiN/HfO2 gate stacks on Ge using low energy plasma-assisted doping with N2 without significant impact on gate capacitance and gate/channel interface trap densities. As required for multi-VT Ge p-FinFETs, controlled change in effective work function up to 180 mV from the near midgap to the near valence band edge of Ge is demonstrated by varying implant dose and energy. Unlike Si gate stacks, increased gate leakage in implanted Ge gate stacks is shown to result from traps created in the HfO2 layer during the implant and exposed to channel carriers due to a low band offset GeO2 interfacial layer (IL). Recovery of gate leakage is demonstrated by substituting GeO2 with an Al2O3 IL. Further, a simple physical model is proposed to extract the work function and oxide charge components of the change in Vfb for varying implant doses and energies.

Laser anneal assisted contact resistivity reduction with post-silicide implantation for 14nm node and beyond

The continuing reduction of contact resistivity (ρC) is a critical challenge for device performance. In this paper the ρC reduction for n-SD (source/drain) is demonstrated using post-silicide implantation of Se or P into Ni(Pt) silicide, with various energies/doses and laser anneal conditions. The improvement of ρC is achieved without sacrificing junction integrity/leakage. Hence laser assisted post-silicide implantation can be a key enabler to realize low silicide contact for n-SD for the 14 nm node and beyond.

Schottky barrier height tuning using P+ DSS for NMOS contact resistance reduction

Nickel silicide (NiSi) contacts are adopted in advanced CMOS technology nodes as they demonstrate several benefits such as low resistivity, low Si consumption and formation temperature. But a disadvantage of NiSi contacts is that they exhibit high electron Schottky barrier height (SBH), which results in high contact resistance (Rc) and reduces the NMOS drive current. To reduce SBH for NMOS, we used phosphorous (P) ion implantation into NiPt silicide with optimized anneal in order to form dopant segregated Schottky (DSS). Electrical characterization was performed using test structures such as Transmission Line Model, Cross-Bridge Kelvin Resistor, Van der Pauw and diodes to extract Rc and understand the effects of P+ DSS on ΦBn tuning. Material characterization was performed using SIMS, SEM and TEM analysis. We report ∼45% reduction in Rc over reference sample by optimizing ion implantation and anneal conditions (spike RTA, milli-second laser anneals (DSA)).

Plasma-assisted As implants for effective work function modulation of TiN/HfO2 gate stacks on germanium

The plasma assisted As doping (PLAD) technique is used to demonstrate multiple flatband voltages (multi-Vfb) on TiN/HfO2 Ge gate stacks for n-FinFET applications. Through detailed studies with varying doses, implant energies, and TiN cap thicknesses, we show that the PLAD As technique can be used to obtain effective work function (EWF) modulation from the near midgap to the conduction band edge (up to 280 meV) of Ge, a key technological requirement for multi-threshold voltage (VT) Ge n-FinFETs. Furthermore, there is no deterioration of key gate stack parameters such as gate leakage, effective oxide thickness, and gate/channel interface trap densities. From secondary ion mass spectroscopy data, we attribute the tuning of EWF to As accumulation and interfacial dipole formation at the TiN/HfO2 interface. The experimental observations are reinforced by ab initio simulations of near-interface As substitutions at the TiN/HfO2 interface. As substitution at N sites near the interface reduces the EWF, making it more suitable for n-MOS applications.The plasma assisted As doping (PLAD) technique is used to demonstrate multiple flatband voltages (multi-Vfb) on TiN/HfO2 Ge gate stacks for n-FinFET applications. Through detailed studies with varying doses, implant energies, and TiN cap thicknesses, we show that the PLAD As technique can be used to obtain effective work function (EWF) modulation from the near midgap to the conduction band edge (up to 280 meV) of Ge, a key technological requirement for multi-threshold voltage (VT) Ge n-FinFETs. Furthermore, there is no deterioration of key gate stack parameters such as gate leakage, effective oxide thickness, and gate/channel interface trap densities. From secondary ion mass spectroscopy data, we attribute the tuning of EWF to As accumulation and interfacial dipole formation at the TiN/HfO2 interface. The experimental observations are reinforced by ab initio simulations of near-interface As substitutions at the TiN/HfO2 interface. As substitution at N sites near the interface reduces the EWF, making it mo...

NMOS contact engineering for CMOS scaling

The 10-7 nm CMOS nodes require that ρc be reduced to <; 2E-9 Ω.cm2. Fermi level for most metals is pinned at mid-gap, resulting in a challenge to decrease SBH. There are several implant solutions, such as thermal implants, that can be leveraged to benefit the FinFET doping of SDE, SD and contact module for scaled CMOS.

Thermal ion implantation for advanced semiconductor processing

Summary form only given. Ion Implantation has been the mainstay for doping of transistors and is used for precise doping for controlling device characteristics including drive current, reducing device leakage, and transistor isolation. Implant has also been used extensively for delivering cost effective multiple threshold voltages required for system on a chip. As devices scaled to 28nm and beyond, cryogenic implants are used extensively to deliver complete amorphization and thus improve dopant activation, interface quality, and leakage reduction. With the advent of Finfets and other 3D transistors, heated implants are integrated to maintain silicon crystallinity and increase activation. In this paper, we will explore the role of thermal implants in enabling transistor scaling.

Selenium segregation optimization for 10 nm node contact resistivity

Contact resistivity (ρ_C) reduction for n-SD (source/drain) with Se⁺ implant was evaluated for different integration schemes. It is found that Se⁺ implant energy is one of the most critical process parameters for ρ_C improvement, achieved by placing the Se⁺ peak close to silicide (TiSi₂ or NiPtSi)/Si interface and minimized implant damage. Recovery of implant damage to silicide and n-SD region was achieved with millisecond laser anneal, while minimizing dopant deactivation. This work demonstrated a viable integration pathway to realize low ρ_C solution for n-SD for 10 nm node.

Cryogenic implantation for source/drain junctions in Ge p-channel (Fin)FETs

We demonstrate record boron activation >4×10²⁰cm^-3 and contact resistivity of 1.7×10^-8Ω-cm² on p⁺-Ge using a single boron implantation process step at cryogenic temperature followed by a low temperature (400^oC) activation anneal. Unlike RT and hot (400^oC) implantation, cryogenic implantation also gives shallower junctions (maintaining lower R_sh) and higher I_ON/I_OFF ratio. Fin TEM and electrical data as well as device simulations for cryogenic, low energy BF₂ implanted epitaxial Ge fins indicate significant and scalable improvement in dopant activation vs room temperature implantation demonstrating feasibility of cryogenic implants for source/drain extensions of future 3D Ge channel p-FinFETs.