Uljana Reinsalu

Code Coverage Analysis using High-Level Decision Diagrams

The paper proposes a novel method of analyzing code coverage metrics on a system representation called high-level decision diagrams (HLDD). Previous works have shown that HLDDs are an efficient model for simulation and test pattern generation. Current paper presents a technique, where fast HLDD based simulation is extended to support seamless code coverage analysis. We show how classical code coverage metrics can be directly mapped to HLDD constructs. In addition, we introduce an observability coverage calculation method using HLDD models. Experiments on ITC99 benchmark circuits indicate the feasibility of the proposed approach.

High-level decision diagram manipulations for code coverage analysis

Previous works have shown that high-level decision diagrams (HLDD-s) are suitable for system representation for analyzing code coverage metrics. This is due to the fact that HLDD models implicitly represent classical code coverage items, such as statement and branch coverage. However, research on the properties of HLDD-s, which contribute to the accuracy of coverage assessment, is missing. Current paper proposes a set of HLDD manipulations in order to generate diagrams that would allow more stringent code coverage measurement without sacrificing performance, i.e., computation time and memory requirements. The techniques include generation of HLDD-trees from Hardware Description Language (HDL)descriptions and two types of HLDD collapsing methods, which are a generalization of the BDD reduction rules. Experiments on ITC99 benchmark circuits show that the code coverage assessment based on the proposed HLDD manipulation is more stringent than what can be achieved with classical methods. At the same time, the model is well scalable because HLDD generation is terminated in the HDL variables.

High-Level Decision Diagrams based coverage metrics for verification and test

The paper proposes High-Level Decision Diagrams (HLDDs) model based structural coverage metrics that are applicable to, both, verification and high-level test. Previous works have shown that HLDDs are an efficient model for simulation and test generation. However, the coverage properties of HLDDs against Hardware Description Languages (HDL) have not been studied in detail before. In this paper we show that the proposed methodology allows more stringent structural coverage analysis than traditional VHDL code coverage. Furthermore, the main new contribution of the paper is a hierarchical approach for condition coverage metric analysis that is based on HLDDs with expansion graphs for conditional nodes. Experiments on ITC99 benchmarks show that up to 14% increase in coverage accuracy can be achieved by the proposed methodology.

HDL-s and FPGA-s in digital design education

To teach digital design efficiently, advantages of the technology should be taken into account. In this paper, an overview is given how hardware description languages (HDL) and field-programmable gate arrays (FPGA) are used at Tallinn University of Technology in digital design education in various related courses. The courses are taught for IT-students with different background - computer engineering, electronics, etc. Observations made and experiences learnt from running the courses over few years are described.

HDL-s for Students with Different Background

In this paper, an overview of teaching hardware description languages (HDL) and related courses at Tallinn University of Technology are presented. The courses are taught for IT-students with different background - computer engineering, electronics, etc. Observations made and experiences learnt from running the courses over few years are described in the second part of the paper.

Register-transfer level deductive fault simulation using decision diagrams

The paper presents a deductive method for register-transfer level fault simulation on the system model of high-level decision diagrams. The method is based on the bit coverage fault model, which has been proven to have a good correspondence with gate-level structural faults. Experiments on ITC99 benchmark circuits have been carried out showing the feasibility of the proposed approach.

Motivation-driven learning processes at the example of embedded systems

This paper addresses motivation-driven learning processes, applied to the field of education in computer engineering. Advantages and drawbacks of classical university teaching approaches are analyzed and evaluated. Based on literature and own experiences a new model for motivation-based learning is derived and presented and illustrated along with a recently developed lecture for Embedded Systems Design. Finally conclusions for concrete future improvements of this course in accordance with the model will be presented.

Experience in increase of practical hours for HDL course

In this paper, an overview of teaching hardware description languages (HDL) at Tallinn University of Technology is presented. The structure of the course was modified by doubling the hours of practical exercises. These changes and their reasons are described in this paper. The course is taught for IT-students with different background — computer engineering, electronics, etc. Observations made and experiences learnt from running the course over few years are described.

Fast RTL Fault Simulation Using Decision Diagrams and Bitwise Set Operations

Efficient fault simulation algorithms for combinational circuits are known for decades. However, sequential fault simulation which is frequently used in test and fault tolerance applications remains a very time-consuming task, in particular for larger circuits. Current paper proposes a new deductive method for Register-Transfer Level (RTL) fault simulation on the system model of high-level decision diagrams. We apply the bit coverage fault model which has proven to provide a good correspondence with gate-level structural faults. Simulation speed-up is achieved due to efficient data structures implemented to perform set operations in the deductive fault simulation algorithm. Experiments on RTL benchmark circuits show that up to two orders of magnitude shorter run-times are achieved with the method in comparison to gate-level fault simulation.

Architectural exploration tasks for on-chip embedded systems

In this paper an idea is proposed, how to simulate a large digital system that could not be mapped onto single FPGA, utilizing the sate-of-the-art features of modern reconfigurable devices. Partial reconfiguration of these devices is the feature for the idea described. Methodology of design flow to any platform is proposed and main problems concerning this methodology are highlighted.