Ulrich Heinle

A capacitance-voltage measurement method for DMOS transistor channel length extraction

This paper reports a new measurement method for extraction of sub-micrometer channel lengths in DMOS transistors. The method is based on capacitance-voltage measurements of the gate to source, gate to p-base and gate to drain capacitances. A channel length of 0.3 /spl mu/m has been measured on DMOS transistors. Numerical device simulations and small-signal capacitance simulations support the results and the measurement principle.

Integration of high voltage devices on thick SOI substrates for automotive applications

Abstract This paper presents a new process for the integration of high voltage devices and low voltage circuitry on thick SOI substrates. Complete dielectric isolation between high voltage and low voltage devices has been realized by deep trench technology. Diodes and transistors with breakdown voltages of 600 and 420 V, respectively, have been demonstrated within these trench structures.

High-power SOI vertical DMOS transistors with lateral drain contacts: Process developments, characterization, and modeling

Silicon-on-insulator (SOI) high-power vertical double-diffused MOS (VDMOS) transistors are demonstrated with a CMOS compatible fabrication process. A new backend trench formation process ensures a defect free device layer. Scanning electron microscope micrographs show that it is nearly free of defects. This has been achieved by moving the trench formation steps toward the end of the process. Our electrical measurements indicate that the transistors are fully functional. Electrothermal simulations show that unclamped inductive switching (UIS) test involves a substantial risk of turning the parasitic bipolar transistor (BJT) on. The UIS test is used to characterize the performance of power devices under unclamped inductive loading conditions. Extreme operating condition can be expected when all the energy stored in the inductor is released directly into device. Our measurements of the fabricated SOI VDMOSFET in the static region are in good agreement with the expected impact of the self-heating on the saturation behavior. The experiments at ambient temperature of 100/spl deg/C show that the break down voltage decreases as the drain voltage increases. This indicates that a parasitic BJT has been turned on.

Vertical High Voltage Devices on Thick SOI with Back-end Trench Formation

We present a new process flow for the integration of vertical high voltage devices on thick SOI. The creation of slip dislocations has been avoided by etching and filling the trenches at the end of the process. Thereby are the trenches not exposed to high temperature steps which trigger the creation of these defects. The electrical characteristics of the fabricated devices are not affected by these process modifications. High voltage transistors with breakdown voltages of 480 V have been fabricated with this new process.

Unclamped inductive switching behaviour of high power SOI vertical DMOS transistors with lateral drain contacts

Unclamped Inductive Switching Behaviour of High-Power SOI Vertical DMOS Transistor with Lateral Drain Contacts

Modeling and characterization of capacitive coupling in trench-isolated structures on SOI substrates

Abstract Trench isolation and SOI substrates have made is possible to integrated high voltage devices together with low voltage circuitry, due to the total galvanic isolation. However, the trenches and the buried oxide of the SOI substrate do affect the total capacitance of the high voltage devices, and give rise to capacitive coupling between adjacent cells. In order to predict those effects, equivalent circuit models are developed in this paper. The models are physically based, and the model parameters are determined by analytical expressions using the geometry of the structures. The models are shown to provide good accuracy in a wide frequency range in comparison to simulated and measured data.

Analysis of the specific on-resistance of vertical high-voltage DMOSFETs on SOI

Integration of high-voltage devices on SOI substrates with deep trench isolation offers the possibility to combine low-voltage circuitry and high-voltage devices on the same chip. However, due to the buried oxide, all device contacts have to be on top of the silicon. Consequently the on-resistance does not scale in the same manner as for conventional vertical devices. In this paper, an analytical model is developed, which accurately predicts the specific on-resistance and its dependency on the number of cells. It is shown that the model predicts an optimum number of cells for a minimal specific on-resistance.

Improved Output Conductance for Low-Voltage Microwave LDMOS Transistors

A low voltage LDMOS transistor has been investigated in terms of output conductance and its affect on and . By process modifications the output conductance has been reduced resulting in =7.8 GHz and =15.6 GHz for a device with =0.75 . The ratio was increased with 32 % and the breakdown voltage increased from 11 V to 16 V.