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Featured researches published by Urmi Ray.


electronic components and technology conference | 2015

First demonstration of drop-test reliability of ultra-thin glass BGA packages directly assembled on boards for smartphone applications

Bhupender Singh; Vanessa Smet; Jaesik Lee; Gary Menezes; Makoto Kobayashi; P.M. Raj; Venky Sundaram; Brian Roggeman; Urmi Ray; Riko Radojcic; Rao Tummala

This paper reports the first demonstration of the drop-test reliability performance of large, ultra-thin glass BGA packages that are directly mounted onto the system board, unlike the current approach of flip-chip assembly of interposers, involving additional organic packages which are then SMT assembled onto boards. The packages, 18.4mm × 18.4mm in size made of 100μm-thick glass, were also successfully assembled, for the first time, in a SMT line. The effect on drop reliability of the glass BGAs with circumferential polymer collars was studied extensively. While the glass BGA packages met the reliability requirements, both with and without polymer collars, the polymer collars were found to further enhance the drop performance, as well as the fatigue life of solders. Finite element modeling was used to understand strain-relief mechanisms and provide design guidelines for reliability. The glass substrates fabrication process along with the formation of polymer collars by spin coating is detailed. The glass package-to-PCB assemblies were formed using SMT-compatible processes with standard equipment, followed by reliability testing through thermal cycling and drop tests. The compiled failure data from drop testing was fitted into a Weibull distribution plot. Comprehensive failure analysis was performed to assess the structural integrity of the glass substrates and identify the predominant failure mechanisms in drop test.


international interconnect technology conference | 2010

3D TSV integration technology challenges for high volume production from fabless supply chain aspect

Shiqun Gu; Urmi Ray; Yiming Li; Arvind Chandrasekaran; Brian Matthew Henderson; Matthew Michael Nowak

Limited battery power for wireless devices demands improvement in power efficiency while enhancing system performance. Traditional semiconductor scaling faces challenges to meet this requirement. 3D integration of multiple chips using through silicon via (TSV) is one of the technologies that can extend the performance scaling trend. However, the semiconductor industry will need to overcome many technology hurdles before 3D TSV integration can be implemented in high volume manufacturing, particularlyfor the fabless supply chain. This paper will review the integration challenges and recent progress in process integration, reliability, yield and cost.


Archive | 2009

Apparatus and Method for Controlling Semiconductor Die Warpage

Xue Bai; Urmi Ray


Archive | 2013

System-in-package with interposer pitch adapter

Dexter Tamio Chun; Jungwon Suh; Urmi Ray; Shiqun Gu


Archive | 2011

Systems and Methods Providing Arrangements of Vias

Shiqun Gu; Matthew Michael Nowak; Durodami J. Lisk; Thomas R. Toms; Urmi Ray; Jungwon Suh; Arvind Chandrasekaran


Archive | 2009

Stress Balance Layer on Semiconductor Wafer Backside

Shiqun Gu; Arvind Chandrasekaran; Urmi Ray; Yiming Li


Archive | 2014

TOROID INDUCTOR IN REDISTRIBUTION LAYERS (RDL) OF AN INTEGRATED DEVICE

Shiqun Gu; Ryan David Lane; Urmi Ray


Archive | 2014

INTEGRATED INTERPOSER WITH EMBEDDED ACTIVE DEVICES

Urmi Ray; Ravindra V. Shenoy; Kwan-Yu Lai; Jon Bradley Lasiter


Archive | 2011

Surface preparation of die for improved bonding strength

Arvind Chandrasekaran; Shiqun Gu; Urmi Ray


Archive | 2010

Barrier Layer On Polymer Passivation For Integrated Circuit Packaging

Shiqun Gu; Urmi Ray; Yiming Li; Arvind Chandrasekaran

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