Uwe Hollerbach

Contact hole reticle optimization by using interference mapping lithography (IML)

The theory of interference mapping lithography (IML) is presented for low k1 (k1<0.4) contact hole imaging. IML with a coherent source is shown to be analogous to methods used in creating a Fresnel lens. With IML for a partially coherent source, the interference map is calculated by using the first eigenfunction of the transmission cross coefficient (TCC). From this interference map, clear 0° AFs and for clear 180° AFs are placed in the optimal location. Thus, IML is a method to place AFs via a model. From the interference map, a method for creating a CPL mask is demonstrated. Using IML, techniques to optimize a binary mask or a CPL mask are presented for maximizing the exposure latitude (EL) or depth of focus (DOF). These techniques are verified with simulation. Using IML for maximum EL, a CPL mask with 100nm (k1=0.39) contacts was created and exposed on an ASML /1100 ArF scanner using NA of 0.75 and Quasar illumination (σin=0.72, σout=0.92, span angle=20°). Measurements on the exposed wafers show that IML CPL results in printing 100nm contacts through pitch (200nm minimum pitch to isolated) with 0.45μm DOF at 10% EL.

RET masks for the final frontier of optical lithography

With immersion and hyper numerical aperture (NA>1) optics apply to the ITRS 2003/4 roadmap scenario (Figure 1); it is very clear that the IC manufacturing has already stepped into the final frontier of optical lithography. Today’s advanced lithography for DRAM/Flash is operating at k1 close to 0.3. The manufacturing for leading edge logic devices does not follow too far behind. Patterning at near theoretical lithography imaging limit (k1=0.25) even with hyper NA optics, the attainable aerial image contrast is marginal at best for the critical feature. Thus, one of the key objectives for low k1 lithography is to ensure the printing performance of critical features for manufacturing. Resolution enhancement technology (RET) mask in combination with hyper NA and illumination optimization is one primary candidate to enable lithography manufacturing at very low k1 factor. The use of rule-based Scattering Bars (SB) for all types of phase-shifting masks has become the de facto OPC standard since 180nm node. Model-based SB OPC method derives from interference mapping lithography (IML) has shown impressive printing result for both clear (gate) and dark field (contact and via) mask types. There are four basic types of RET mask candidates for 65nm node, namely, alternating phase-shifting mask (altPSM), attenuated PSM (attPSM), chromeless phase lithography (CPL) PSM, and double dipole lithography (DDL) using binary chrome mask. The wafer printing performances from CPL and DDL have proven both are strong candidates for 45nm nodes. One concern for using RET masks to target 45 nm nodes is likely to be the scaling for SB dimension for 4X mask. To assist imaging effectively with high NA, SB cannot be too small in width. However, for SB to be larger than sub-resolution, they can easily cause unwanted SB printing. The other major concern is the unwanted side lobe printing. This may occur for semi-dense pitch ranges under high NA and strong off-axis-illumination (OAI). Looking ahead, for manufacturing at 45 nm and 32nm nodes, one challenge is to break through the so-called k1 barrier (0.25). Multiple exposure schemes in conjunction with RET masks is our proposed solution

Near-0.3 k1 full pitch range contact hole patterning using chromeless phase lithography (CPL)

Resolution Enhancement Techniques (RET), or low k1 imaging, has been deployed successfully to extend the resolution limits of optical lithography significantly below half-λ for todays poly gate mask in the state-of-the-art manufacturing processes. However, achieving satisfactory contact hole patterning through the full pitch range required for the 90nm and 65nm technology nodes has greatly challenged the leading process development effort. Currently, attenuated PSMs with transmission between 5% and 9% are used to enhance the resolution of dark field contact hole patterns. Using conventional illumination with a low sigma, which is the common method employed for att-PSM, limits the minimum pitch that can be resolved on the wafer. By using off-axis illumination (OAI) it is possible to image smaller pitches. However, the same attributes that enhance imaging for dense patterns severely degrade the imaging of isolated patterns. Using Chromeless Phase Lithography (CPL), sub-wavelength isolated contact patterns can be imaged using strong off-axis illumination, such as Quasar, dipole and double dipole, etc. By applying modeled sub-resolution and non-printing features, we found it is possible to achieve very high-resolution contact imaging with exceptional process latitude. Both phase shifted and non-phase shifted patterns can be much larger than sub-resolution assist features (or anti-Scattering Bars) used on dark field binary reticles (~three times larger), making the reticle pattern easier to manufacture. Using this method, sub-wavelength bright patterns on a dark field can be imaged through the full pitch range. We have shown that it is feasible to push the contact resolution limit to 0.33 k1 or smaller.

Eigen-decomposition-based models for model OPC

Model based optical proximity correction (OPC) to enhance image fidelity and process robustness has become one of the most critical components that enable optical lithography tackling 45nm node and beyond. To meet the challenges imposed by the previously unthinkable low k1 for manufacturing with most stringent dimension control requirements, a capable model OPC to meet such an aggressive lithography challenges has been urgently called upon. In addition to providing better accuracy for the currently implemented process technologies, the new model OPC must work well with Chromeless Phase Lithography (CPL) in which the topography on the mask is rather significant, and Double Dipole Lithography (DDL) in which two masks and two exposures are needed. It must also be able to intelligently take into account the effect from the more aggressive illuminations, such as customer designed illuminator and experimental measured illuminator profile from the scanners. This capability is very important since the real illuminator pupil can impact OPC accuracy. The physical and mathematical foundation of the model must be well thought of to meet the requirement for the above-mentioned applications. We have developed a novel Eigen Decomposition Model (EDM) for model OPC treatment applicable for all types of advanced binary and phase-shifting masks. Together with a full 2D model calibration and verification methodology, the results from this new model OPC have proven to achieve a superb CD accuracy with versatile capabilities for extreme low k1 imaging application. This report will explain how the model works with example applications and actual wafer results.

Contact and via hole mask design optimization for 65-nm technology node

For advance semiconductor manufacturing, imaging contact and via layers continues to be a major challenge for 65nm node lithography and beyond. As a result, much effort is being placed on reducing the k1 for hole patterning to the range of 0.35 - 0.40. However, the consequences of operating at such low k1 values are a small DOF, reduced exposure latitude, and high MEF. To achieve this level of k1, it is necessary to employ resolution enhancement techniques that require phase shifting reticles and/or strong off axis illumination. Recent results show that by using strong off axis illumination to achieve resolution for the dense pitch contacts and by adding subresolution scattering bars for the semi dense to isolated, it is possible to achieve contact hole imaging through the entire pitch range.[1] To generate such reticle designs, the current technique commonly used is to apply a set of rules to define the assist features (scattering bars, anti-scattering bars, non-printing assist features, phase shifted and non-phase shifted) through pitch, whether for binary or attenuated phase shifting reticles. But this approach is not capable of deriving correct assist feature placement for the entire range of pitches and for the randomly placed contact holes that occur in actual device patterns. The objective of this work is to define the necessary methodology for creating binary, attPSM, ternary HTPSM, and CPLTM reticle designs containing assist features for contact patterns that are representative of actual device patterns that will be used in production at the 65nm node and contain effectively randomly placed contacts over a wide range of pitches from dense to isolated. To overcome the problem of deriving assist features for randomly placed contacts at pitches from semi-dense to isolated, IMLTM Technology was used which is a modeling algorithm based on mapping out the interference that occurs at the image plane as a result of the proximity effects of the target contact pattern.[2,3] This technique provides a model-based approach for placing all types of assist features for the purpose of enhancing the resolution of the target pattern and it can be applied to any reticle type including binary, attPSM, altPSM, ternary HTPSM, and CPL. Using reticle designs created from implementing automated algorithms based on IML, wafer printing results are measured and we examine the critical issues related to contact layer RETs including through pitch process windows, overlapping process window, controlling side lobe printing, contact patterns with odd symmetry, forbidden pitch regions, printing of the assist features, MEF, and reticle manufacturing constraints.

Effects of advanced illumination schemes on design manufacturability and interactions with optical proximity corrections

ABSTRACT As advanced source illumination options become available for production implementation, at the 150 nm and 130 nmtechnology nodes, non-linear effects are introduced in the design shrink-path. In previous technologies, in particular 250 and180 nm, partial coherence settings are used as a method to control mono-dimensional CD variations among features withdifferent pitches (iso-dense bias). Source optimization becomes a function of the design pattern to be imaged and of theOptical Proximity Corrections (OPC) applied to this design. The advent of Quadrupole, QuasarTM and Custom IlluminationApertures enables and enhances the use of Optical Extension (OE) techniques to image features down to half of the KrF (248nm) wavelength, but imposes stringent geometrical restrictions on the design, which are not currently well understood. Ourwork presents a novel methodology for analyzing effects of source illumination variations on full chip design layouts,extending and generalizing the concept of Process Window. By combining a powerful full-chip imaging simulator and anilluminator design tool, a very large parameter space of design geometries can be explored. Comparison between the desiredand the actually imaged patterns is performed, yielding statistically significant CD errors. The analysis of this very largenumber of printability data points, covering the whole design pattern, allows the classification of critical geometries, i.e. theportions of the design which are process window limiting. Our methodology not only provides an illumination optimizationtool for the lithographer, but, above all, highlights the need for Manufacturability Verification performed early at the physicallayout stage of the semiconductor design process. In particular, a design verification application is shown, where progressivelinear shrinks of a given layout are matched against optimal image settings. Quantitative analysis of the resulting patternfailure modes provides a direct feedback for the layout designer.Keywords: Manufacturability Verification, Lithography, Semiconductor Processing, OPC, DFM, Physical Verification,Optical Extensions, Process Window.

Model-based scattering bars implementation for 65nm and 45nm nodes using IML technology

Scattering Bars (SB) OPC, together with optimized illumination, is no doubt one of the critical enablers for low k1 lithography manufacturing. The manufacturing implementation of SB so far has been mainly based on rule-based approach. While this has been working well, a more effective model-based approach is much more desired lithographically for manufacturing at 65nm and 45nm nodes. This is necessary to ensure sufficient process margin using hyper NA for patterning random IC design. In our model-based SB (M-SB) OPC implementation, we have based on the patented IML Technology from ASML MaskTools. In this report, we use both dark field contact hole and clear field poly gate mask to demonstrate this implementation methodology. It is also quite applicable for dark field trench masks, such as local interconnect mask with damascene metal. For our full-chip implementation flow, the first step is to determine the critical design area and then to proceed with NA and illumination optimization. We show that, using LithoCruiser, we are able to select the best NA in combination with optimum illumination via a Diffraction Optical Element (DOE). The decision to use a custom DOE or one from the available DOE library from ASML can be made based on predicted process performance and cost effectiveness. With optimized illumination, it is now possible to construct an interference map for the full-chip mask pattern. Utilizing the interference map, M-SB OPC is generated. Next, model OPC can be applied with the presence of M-SB for the entire chip. It is important to note here, that from our experience, the model OPC must be calibrated with the presence of SB in order to achieve the desired accuracy. We report the full-chip processing benchmark using MaskWeaver to apply both M-SB and model OPC. For actual patterning performance, we have verified the full chip OPC treatment using SLiC, a DFM tool from Cadence. This implementation methodology can be applied to binary chrome mask, attenuated PSM, and CPL.

Manufacturing implementation of IML technology for 45 nm node contact masks

For advance semiconductor manufacturing, patterning contact and via mask layers continue to be major challenge. As a result, RETs beyond the current standard 6% attPSM technology are being pursued with a goal of reducing the k1 for hole patterning to the range of 0.35 - 0.40. IML Technology has shown promising results as a possible solution which employs strong off axis illumination (OAI) to achieve the resolution for the dense pitch contacts and the use of sub-resolution scattering bars (SB) for the semi dense to isolated contacts. At the 45nm node, placing SB by simply applying a set of rules is not sufficient for deriving the correct assist feature placements for the entire range of pitches and for the complex, randomly placed contacts that occur in actual device patterns. IML Technology utilizes modeling to locate where SB should be placed and in the case of high transmission ternary PSM (HTPSM) and CPL, defines the phase of the SB relative to the contacts being imaged. To generate such reticle designs, highly complex interference maps are calculated and from this optical interference behavior, the reticle pattern is derived. Previously, the reticle pattern derived in such a manner was extremely complex raising a question as to how feasible such an approach would be in a manufacturing environment. New algorithms which simplify the mask pattern while maintaining the resolution enhancement capability of IML have been developed. The objective of this work is to demonstrate a manufacturing methodology that utilizes IML Technology and is capable of meeting the requirements for the 45nm node designs. We will explore the application of this method 6% attPSM and CPL reticle designs which containing contact patterns that are representative of production devices. To define the SB for what are effectively randomly placed contacts over a wide range of pitches from dense to isolated, IML Technology is used. This modeling algorithm is based on mapping out the interference that occurs at the image plane as a result of the proximity effects of the target contact pattern. This technique provides a model-based approach for placing all types of assist features on both clear field and dark field patterns for the purpose of enhancing the printing resolution of the target pattern and it can be applied to any reticle type including binary, attPSM, altPSM, ternary HTPSM, and CPL. By implementing newly developed algorithms, simplified reticle patterns are generated which maintain the optimum SB placements determined by the IML process.

OPC model calibration for CPL patterning at extreme low k1

Model based optical proximity correction (OPC) to enhance image fidelity and process robustness has become one of the most critical components that enable the low k1 optical lithography. To meet the challenges imposed by the previously unthinkable low k1 for manufacturing with most stringent dimension control requirements, a capable OPC model to meet such an aggressive lithography challenges has been urgently called upon. In addition to providing better accuracy for the currently implemented process technologies, the new OPC model must work well with Chromeless Phase Lithography (CPL) in which the topography on the mask is rather significant, and Double Dipole Lithography (DDL) in which two masks and two exposures are needed. It must also be able to intelligently take into account the effect from the more aggressive illuminations, usch as customer designed illuminator and experimental measured illuminator profile from the scanners. The physical and mathematical foundation of the model must be well thought of to meet the requirements for the above-mentioned applications. We have extended our Eigen Decomposition Model (EDM) for model OPC treatment into the high NA regime, in which the vector characteristics of light and thin film stack are taken into account. For CPL calibration, it has been found that 3D mask topography effect cannot be ignored in order to achieve satisfactory model accuracy.

Effects of off-axis illumination and scattering-bar optical proximity correction on the impact of lens aberration on 130-nm polygate mask: a simulation study

A simulation study has been performed to look at improving the imaging of a 130nm poly gate mask design. For this lithography process, we have chosen 6 percent attenuated PSM applied with scattering-bar optical proximity correction (SB-OPC) using 248 nm exposure wavelength. We compare the process window performance of off-axis illuminations (OAI) such as QUASAR and annular to a conventional on-axis illumination. Sampled lens aberrations were introduced to the simulation model to evaluate the impact of illumination settings. Simulations show benefits of combining SB-OPC technology with OAI on the performance of 130nm poly gate line features in the presence of known lens aberrations. For this simulation study, we have used our WaveMaster software tool to automate the SOLID-C simulation loops that includes multiple pre-selected line features form an actual poly gate mask design, five different lens aberration Zernike data sets, and three illumination settings.