Ji-Soong Park

An efficient rule-based OPC approach using a DRC tool for 0.18 /spl mu/m ASIC

The increasing complexity and data volume of VLSI designs demand an efficient optical proximity correction (OPC) technique. In this paper, we address the issues related to the gate bridge, which is serious in sub-quarter micron technology, and the wide range of contact CD (Critical Dimension) variation. We present the efficient gate CD control method by introducing the critical area correction. In addition, the contact CD variation is reduced under the target CD range due to the combination of the contact biasing and the process calibration. The correction time and output data volume are drastically reduced by the hierarchical data manipulation using a DRC (Design Rule Check) tool, which basically exploits the characteristics of the design layers in ASICs. The newly proposed incremental on-line violation filtering method also reduces the correction cycle time significantly.

Hybrid PPC methodology using multi-step correction and implementation for the sub-100-nm node

As semiconductor devices are scaled down to the sub-100nm node, the fine control of ACLV (across-chip line-width variation) to improve the performance of chips and the expansion of the process window to enhance yield are required. One of the techniques reducing ACLV is MPPC (model-based process proximity correction). However, it increases pattern complexity and does not guarantee enough process windows. Therefore, we propose a HPPC (hybrid PPC) methodology combining RPPC (rule-based PPC) and MPPC, which correct the gate on active by MPPC for device performance and the field gate by RPPC for process window. In addition, we optimize SRAF (sub-resolution assist feature) design to improve process windows further at the full chip level and apply the multi-step correction, which corrects optical and etch proximity effects separately to minimize ACLV. As the result of the application to the 90nm logic gate, we achieve over 0.3um DOF (depth of focus) and the line-width variation within ±5% of the target CD (critical dimension).

Optical proximity correction considering mask manufacturability and its application to 0.25-μm DRAM for enhanced device performance

A practical optical proximity correction (OPC) method is introduced and applied to 0.25 micrometers DRAM process in order to reduce the gate critical dimension (CD) variations across the exposure field. A variable threshold model is made and evaluated to enhance the model accuracy. This model takes maximum 2X computation time compared with the constant threshold model. The proposed OPC methodology considering both process effects and mask manufacturability simultaneously is discussed in view of the gate line CD variation. The correction segments of a pattern are optimized considering mask manufacturability. Patterns with jog sizes larger than 0.4 micrometers are inspect able with KLA35UV. The OPC results exhibited 60 percent reduction of gate CD variation, 90 percent matching of mean-to-target CD, and 15 percent improvement of circuit performance.

A hybrid PPC method based on the empirical etch model for the 0.14/spl mu/m DRAM generation and beyond

The hybrid PPC (process proximity correction) has been one of the inevitable methods for the sub-wavelength lithography to satisfy the requirements of CD control and yield improvement. In this paper, an effective methodology for hybrid PPC is presented to reduce the data volume and the complexity of patterns and to enhance the accuracy of correction. The selective engine in the flow of hybrid PPC classifies the gate patterns into the areas of model-based and rule-based PPC considering a device performance, a model accuracy, and the extension of the contact overlap margin. Furthermore, the effective method of an empirical model is exploited to compensate the nonlinear etch proximity effect. The statistical method based on the real pattern geometry is also constructed to reflect the process issues in real manufacturing. From this work with the 1 nm correction grid, 22% of the additional reduction in the intra-die CD variation compared with the rule-based PPC has been achieved.

Robust and fast OPC approach for metal interconnects of 0.13um logic devices

Insufficient metal overlaps over contacts and/or vias impact serious yield loss especially in the borderless-contact- style random logic devices. Vias which are not fully covered by interconnects cause not only the functional error due to the high via resistance but also the reliability problem such as electro migration. It is not sufficient to compensate only optical proximity effects such as line-end shortening and corner rounding for the overlap margin. Since mis-alignment between interconnects and over/underlying features is not negligible even using an advanced alignment system of step and scanner. Therefore, the need for aggressive OPC is increased to cope with the proximity effect and overlay error in metal interconnects. The proposed OPC approach gives a robust metal overlap with fast runtime and allowable data complexity by selective correction for the improperly overlapped contacts and vias. Experimental results for the test design show that the correction time of the metal interconnects takes 11 hours at HP5600 system by applying the proposed correction algorithm.

MPC model validation using reverse analysis method

It became more challenging to guarantee the overall mask Critical Dimension (CD) quality according to the increase of hot spots and assist features at leading edge devices. Therefore, mask CD correction methodology has been changing from the rule-based (and/or selective) correction to model-based MPC (Mask Process Correction) to compensate for the through-pitch linearity and hot spot CD errors. In order to improve mask quality, it is required to have accurate MPC model which properly describes current mask fabrication process. There are limits on making and defining accurate MPC model because it is hard to know the actual CD trend such as CD linearity and through-pitch owing to the process dispersion and measurement error. To mitigate such noises, we normally measure several sites of each pattern types and then utilize the mean value of each measurement for MPC modeling. Through those procedures, the noise level of mask data will be reduced but it does not always guarantee improvement of model accuracy, even though measurement overhead is increasing. Root mean square (RMS) values which is usually used for accuracy indicator after modeling actually does not give any information on accuracy of MPC model since it is only related with data noise dispersion. In this paper, we reversely approached to identify the model accuracy. We create the data regarded as actual CD trend and then create scattered data by adding controlled dispersion of denoting the process and measurement error to the data. Then we make MPC model based on the scattered data to examine how much the model is deviated from the actual CD trend, from which model accuracy can be investigated. It is believed that we can come up with appropriate method to define the reliability of MPC model developed for optimized process corrections.

Reduction of MDP complexity through the application of OASIS based data flow

In the IC process, the designed circuit pattern is drawn onto film or glass plate as a photo mask. This original mask is used to transform its transparent pattern onto semiconductor wafers by optical projection. To make photo mask we should convert the design data into a format that the e-beam write tool can understand. This MDP (Mask Data Preparation) process is getting more and more complicated to support many kinds of e-beam data format which is required not only for each electron beam writers but die to database inspection tools. It gives us a burden to treat various MDP flow and this may impact on turn around time (TAT). Therefore, it becomes more necessary to make MDP flow simpler by unifying the various mask data formats. Moreover it is required to suppress huge data volume due to design rule shrink and aggressive OPC. To address these issues, the Open Artwork System Interchange Standard (OASISTM) has been approved by the EDA industry and is officially announced by SEMI Data Path Task Force. OASIS data format allows the reduction in file size compared to GDSII while the processing time such as MRC and MDP is not influenced. Also OASIS is effective in reducing complexity of mask data preparation flow. In this paper, the implementation of OASIS format within mask data preparation flow will be discussed and experimental results of OASIS-based data flow will be shown with comparing to traditional GDSII/MEBES-based data flow.

The application of phase grating to CLM technology for the sub-65nm node optical lithography

As a promising technology for sub-65nm node optical lithography, CLM(Chrome-Less Mask) technology among RETs(Resolution Enhancement Techniques) for low k1 has been researched worldwide in recent years. CLM has several advantages, such as relatively simple manufacturing process and competitive performance compared to phase-edge PSMs. For the low-k1 lithography, we have researched CLM technique as a good solution especially for sub-65nm node. As a step for developing the sub-65nm node optical lithography, we have applied CLM technology in 80nm-node lithography with mesa and trench method. From the analysis of the CLM technology in the 80nm lithography, we found that there is the optimal shutter size for best performance in the technique, the increment of wafer ADI CD varied with patterns pitch, and a limitation in patterning various shapes and size by OPC dead-zone - OPC dead-zone in CLM technique is the specific region of shutter size that dose not make the wafer CD increased more than a specific size. And also small patterns are easily broken, while fabricating the CLM mask in mesa method. Generally, trench method has better optical performance than mesa. These issues have so far restricted the application of CLM technology to a small field. We approached these issues with 3-D topographic simulation tool and found that the issues could be overcome by applying phase grating in trench-type CLM. With the simulation data, we made some test masks which had many kinds of patterns with many different conditions and analyzed their performance through AIMS fab 193 and exposure on wafer. Finally, we have developed the CLM technology which is free of OPC dead-zone and pattern broken in fabrication process. Therefore, we can apply the CLM technique into sub-65nm node optical lithography including logic devices.

Hybrid PPC methodology and implementation in the correction of etch proximity

In the exponential drive to go to the smaller feature size, the control of the line width variation becomes more important than ever before. Hybrid PPC (Process Proximity Correction) has been one of the indispensable methods to satisfy the requirements of CD control and yield improvement. In this paper, an effective methodology for hybrid PPC is presented to reduce the data volume and the complexity of patterns and to enhance the accuracy of correction. The selective engine in the hybrid PPC flow classifies the gate patterns into the areas of model-based and rule-based PPC considering a device performance, a modeling accuracy, and the extension of the contact overlap margin. The effective method of edge pattern modeling is exploited to compensate the nonlinear etch proximity effect in the asymmetrical pattern configuration. Using the hybrid PPC method with the 1 nm correction grid, 22% of the additional reduction in the intra-die CD variation compared to the rule-based PPC with 5 nm correction grid has been achieved.

Improvement of metal photo process margin with OPC and CMP for 0.14 μm DRAM technology node and beyond

In this paper, we report highly effective Optical Proximity Correction (OPC) techniques to improve the process margin in the photo lithography process of metal layer, which can be applied to 0.14 micrometer DRAM technology node and beyond. The proposed test pattern reflects the optical limitation of each situation, the rules can be established by simply investigating the test patterns which solves the problems such as lack of contact overlap margin, line-end shortening, and size reduction in isolated and island patterns. This sophisticated rule is considering the vertical environment as well. Thanks to systematic sequence for rule extraction, we could minimize additional burdens such as error occurrence, rule set-up time, data volume, manufacturing time of mask. By applying this method, DOF margin of metal layer could be improved from 0.4 micrometer to beyond 0.6 micrometer, which provides sufficient process window for mass production of 0.14 micrometer DRAM technology. In addition, we also confirmed that the new OPC technology could be extended to the metal layer of 0.11 micrometer DRAM.