V. Deshpande
IBM
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Publication
Featured researches published by V. Deshpande.
Applied Physics Letters | 2012
B. Roche; B. Voisin; X. Jehl; Romain Wacquez; M. Sanquer; M. Vinet; V. Deshpande; B. Previtali
A dual mode device behaving either as a field-effect transistor or a single electron transistor (SET) has been fabricated using silicon-on-insulator metal oxide semiconductor technology. Depending on the back gate polarisation, an electron island is accumulated under the front gate of the device (SET regime), or a field-effect transistor is obtained by pinching off a bottom channel with a negative front gate voltage. The gradual transition between these two cases is observed. This dual function uses both vertical and horizontal tunable potential gradients in non-overlapped silicon-on-insulator channel.
symposium on vlsi technology | 2015
V. Djara; V. Deshpande; Emanuele Uccelli; N. Daix; Daniele Caimi; C. Rossel; Marilyne Sousa; Heinz Siegwart; Chiara Marchiori; J.M. Hartmann; K.-T. Shiu; C.-W. Weng; M. Krishnan; Michael F. Lofaro; R. Steiner; Devendra K. Sadana; D. Lubyshev; A. Liu; Lukas Czornomaz; Jean Fompeyrine
We report on the first demonstration of ultra-thin body (50 nm), low defectivity 200 mm InGaAs-on-insulator (-OI) fabricated by direct wafer bonding technique (DWB) as well as a replacement gate process for self-aligned fully depleted InGaAs MOSFETs. These combined achievements highlight the viability of our approach for the VLSI integration of InGaAs at advanced nodes. Short channel replacement gate (RMG) and Gate-first (GF) FETs are reported for the first time using InGaAs-OI wafers with a 120nm contact-to-contact pitch. Record ION (118 μA/μm) at fixed operating voltage of 0.5V for InGaAs devices on Si is achieved on 50-nm-Lg RMG FinFETs. Both schemes feature highly scaled fins (down to 15 nm). Compared to a GF integration flow, RMG devices exhibit better Ion and DIBL characteristics. We also demonstrate FETs with 70 nm contacts and 120 nm pitch achieving high-ION.
symposium on vlsi technology | 2015
Lukas Czornomaz; Emanuele Uccelli; Marilyne Sousa; V. Deshpande; V. Djara; Daniele Caimi; Marta D. Rossell; Rolf Erni; Jean Fompeyrine
We report on the first demonstration of the CMOS-compatible integration of high-quality InGaAs on insulator (InGaAs-OI) on Si substrates by a novel concept named Confined Epitaxial Lateral Overgrowth (CELO). This method, based on selective epitaxy, only requires the use of standard large-area silicon substrates and typical CMOS processes. It enables the fabrication of InGaAs-OI starting from both bulk and SOI Si wafers. The InGaAs epitaxial structures are characterized by a very low defectivity, and can fulfill the requirements of both ultra-thin-body and fins-based advanced CMOS nodes. Gate-first self-aligned FinFETs (100-nm-long gate, 50-nm-wide fins and 250-nm-wide plug-contacts) with excellent electrical characteristics comparable to start-of-the-art InGaAs MOSFETs on Si are demonstrated, highlighting that this new concept has significant potential to enable introduction of high-mobility channel materials in high-volume manufacturing of advanced CMOS nodes.
international electron devices meeting | 2015
V. Deshpande; V. Djara; E. O'Connor; Pouya Hashemi; Karthik Balakrishnan; Marilyne Sousa; Daniele Caimi; A. Olziersky; Lukas Czornomaz; Jean Fompeyrine
We demonstrate, for the first time, scaled hybrid inverters built in a 3D Monolithic (3DM) CMOS process featuring short-channel replacement metal gate (RMG) InGaAs-OI wide-fin/planar nFET top layer and SiGe-OI fin pFET bottom layer. We achieve state-of-the-art device integration, using raised source drain (RSD) on both levels and silicide on bottom pFETs. Bottom SiGe-OI pFETs are scaled down to sub-20 nm gate length (Lg) using a gate first (GF) flow, and top InGaAs nFETs scaled down to sub-50 nm Lg are fabricated using a RMG process. With an optimized thermal budget for the top InGaAs nFETs, we show that the 3D integration scheme does not degrade the performance of the bottom SiGe-OI pFETs. Finally, we demonstrate well-behaved integrated inverters with sub-50 nm Lg down to VDD = 0.25 V.
symposium on vlsi technology | 2010
Romain Wacquez; M. Vinet; Mathieu Pierre; B. Roche; X. Jehl; O. Cueto; J. Verduijn; G. C. Tettamanzi; S. Rogge; V. Deshpande; B. Previtali; C. Vizioz; S. Pauliac-Vaujour; C. Comboroure; N. Bove; O. Faynot; M. Sanquer
Although single dopant signatures have been observed at low temperature [1–2], the impact on transistor performance of a single dopant atom at room temperature is not yet well understood. Here, for the first time, we provide an in-depth understanding of single dopant influence on NMOSFETs characteristics by linking low and room temperature transport. We demonstrate that, for gate length of 30 nm and below (channel length down to 10 nm), the presence of a single dopant dramatically alters the subthreshold behaviour when the dopant is located in the middle of the channel. Moving the dopants away from the channel leads to enhanced variability above the threshold voltage Vt.
european solid state device research conference | 2012
V. Deshpande; Sylvain Barraud; X. Jehl; Romain Wacquez; M. Vinet; R. Coquand; B. Roche; B. Voisin; François Triozon; Christian Vizioz; L. Tosti; B. Previtali; P. Perreau; T. Poiroux; M. Sanquer; O. Faynot
For the first time we evidence the transition from a MOSFET operation to Single Electron Transistor (SET) behavior at 300 K in scaled nanowires (down to 5 nm width). In this paper we show that on scaling nanowire width from 20 nm down to 5 nm regime, together with achieving excellent short channel effect control (DIBL=12 mV/V for LG=20 nm), we hit a dramatic transition in transport mechanism from monotonously increasing to periodically peaked ID-VGs. This transition is brought about by process induced channel potential variability (due to disorder) in nanowires and poses a challenge to further scaling. However, we show that it provides an exciting opportunity to cointegrate Single Electron Transistors with high-k/metal gate operating at room temperature (at VD=±0.9 V!) with the state-of-the-art nanowire MOSFETs enabling large scale manufacturing of beyond Moore devices.
Japanese Journal of Applied Physics | 2017
V. Deshpande; V. Djara; Eamon O’Connor; Pouya Hashemi; Thomas Morf; Karthik Balakrishnan; Daniele Caimi; Marilyne Sousa; Jean Fompeyrine; Lukas Czornomaz
Three-dimensional (3D) monolithic integration can enable higher density and has the potential to stack independently optimized layers at transistor level. Owing to high mobility and lower processing temperatures, InGaAs is well-suited to be used as the top layer channel material in 3D monolithic integration along with Si/Si(Ge) FETs. A review of recent progress to develop InGaAs-on-Si(Ge) 3D Monolithic technology is presented here.
symposium on vlsi technology | 2016
Lukas Czornomaz; V. Djara; V. Deshpande; E. O'Connor; Marilyne Sousa; Daniele Caimi; Kangguo Cheng; Jean Fompeyrine
We report the first demonstration of InGaAs/SiGe CMOS inverters and dense SRAM arrays on Si, fabricated with InGaAs selective epitaxy and standard front end of line (FEOL) processes. This novel and scalable CMOS integration scheme enables InGaAs nFET fabrication in close proximity to SiGe pFETs (down to 25 nm spacing), resulting in 6T-SRAM arrays having a minimum cell size below 0.45 μm2. This scheme can be combined with any bulk Si or SOI-based planar or fin technology, and is compatible with standard large-area Si substrate. Individual InGaAs nFETs and SiGe pFETs are fabricated with a standard self-aligned CMOS-compatible process flow and feature LG scaled down to 35 nm. Moreover, the InGaAs nFET process flow includes selective epitaxy, raised source/drain (RSD) and high-k/metal gate (HKMG) modules. Finally, we report electrical characterization of isolated FETs and inverters as well as dense SRAM cells with planar and fin- FETs.
joint international eurosoi workshop and international conference on ultimate integration on silicon | 2016
V. Deshpande; V. Djara; E. O'Connor; Daniele Caimi; Marilyne Sousa; Lukas Czornomaz; Jean Fompeyrine; Pouya Hashemi; Karthik Balakrishnan
We report the first RF characterization of short-channel replacement metal gate (RMG) InGaAs-OI nFETs built in a 3D Monolithic (3DM) CMOS process. This process features RMG InGaAs-OI nFET top layer and SiGe-OI fin pFET bottom layer. We demonstrate state-of-the-art device integration on both levels. The bottom layer SiGe-OI pFETs are fabricated with a Gate-First (GF) process with fins scaled down to ∼15 nm width and featuring epitaxial raised source drain (RSD) and silicide. The top layer InGaAs nFETs are fabricated with a RMG process featuring a self-aligned epitaxial raised source drain (RSD). We show that the 3D monolithic integration scheme does not degrade the performance of the bottom SiGe-OI pFETs owing to an optimized thermal budget for the top InGaAs nFETs. From the RF characterizations performed (post-3D monolithic process) on multifinger-gate InGaAs-OI nFETs, we extract a cut-off frequency (Ft) of 16.4 GHz at a gate-length (Lg) of 120 nm. Measurements on various gate lengths shows increasing cut-off frequency with decreasing gate-length.
joint international eurosoi workshop and international conference on ultimate integration on silicon | 2016
L. Pirro; Hyung Jin Park; Irina Ionica; M. Bawedin; Sorin Cristoloveanu; Lukas Czornomaz; V. Djara; V. Deshpande
Doped InGaAs were characterized using a revisited pseudo-MOSFET configuration. Two different conduction mechanisms were evidenced: volume and interface. The impact of film thickness, channel width and length is evaluated. Measurements at low temperatures complete the analysis.