Emanuele Uccelli

An integration path for gate-first UTB III-V-on-insulator MOSFETs with silicon, using direct wafer bonding and donor wafer recycling

In this work we demonstrate for the first time that the excellent thermal stability of ultra-thin body (UTB) III-V heterostructures on silicon provides a path for the cointegration of self-aligned In0.53Ga0.47As MOSFETs with silicon. We first demonstrate that the transfer of high-quality InGaAs / InAlAs heterostructures (tch <; 10 nm) can be achieved by direct wafer bonding and hydrogen-induced thermal splitting, and that the donor wafer can be recycled for a cost-effective process. The thermal stability of the bonded layer enables to integrate UTB III-V MOSFETs at 500 nm pitch using a gate-first flow featuring raised source/drain (S/D) grown at 600oC. The expected benefit of an UTB structure is benchmarked by comparing sub-threshold slope (SS) and drain-induced-barrier-lowering (DIBL) against state-of-the-art III-V-o-I or Tri-Gate FET data.

An InGaAs on Si platform for CMOS with 200 mm InGaAs-OI substrate, gate-first, replacement gate planar and FinFETs down to 120 nm contact pitch

We report on the first demonstration of ultra-thin body (50 nm), low defectivity 200 mm InGaAs-on-insulator (-OI) fabricated by direct wafer bonding technique (DWB) as well as a replacement gate process for self-aligned fully depleted InGaAs MOSFETs. These combined achievements highlight the viability of our approach for the VLSI integration of InGaAs at advanced nodes. Short channel replacement gate (RMG) and Gate-first (GF) FETs are reported for the first time using InGaAs-OI wafers with a 120nm contact-to-contact pitch. Record ION (118 μA/μm) at fixed operating voltage of 0.5V for InGaAs devices on Si is achieved on 50-nm-Lg RMG FinFETs. Both schemes feature highly scaled fins (down to 15 nm). Compared to a GF integration flow, RMG devices exhibit better Ion and DIBL characteristics. We also demonstrate FETs with 70 nm contacts and 120 nm pitch achieving high-ION.

Confined Epitaxial Lateral Overgrowth (CELO): A novel concept for scalable integration of CMOS-compatible InGaAs-on-insulator MOSFETs on large-area Si substrates

We report on the first demonstration of the CMOS-compatible integration of high-quality InGaAs on insulator (InGaAs-OI) on Si substrates by a novel concept named Confined Epitaxial Lateral Overgrowth (CELO). This method, based on selective epitaxy, only requires the use of standard large-area silicon substrates and typical CMOS processes. It enables the fabrication of InGaAs-OI starting from both bulk and SOI Si wafers. The InGaAs epitaxial structures are characterized by a very low defectivity, and can fulfill the requirements of both ultra-thin-body and fins-based advanced CMOS nodes. Gate-first self-aligned FinFETs (100-nm-long gate, 50-nm-wide fins and 250-nm-wide plug-contacts) with excellent electrical characteristics comparable to start-of-the-art InGaAs MOSFETs on Si are demonstrated, highlighting that this new concept has significant potential to enable introduction of high-mobility channel materials in high-volume manufacturing of advanced CMOS nodes.

Vertical InAs-Si Gate-All-Around Tunnel FETs Integrated on Si Using Selective Epitaxy in Nanotube Templates

In this paper, we introduce p-channel InAs-Si tunnel field-effect transistors (TFETs) fabricated using selective epitaxy in nanotube templates. We demonstrate the versatility of this approach, which enables III-V nanowire integration on Si substrates of any crystalline orientation. Electrical characterization of diodes and of TFETs fabricated using this method is presented; the TFETs exhibit a good overall performance with on-currents, Ion of 6 μA/μm (|VGS| = |VDS| = 1 V) and a room-temperature subthreshold swing (SS) of ~160 mV/dec over at least three orders of magnitude in current. Temperature-dependent measurements indicate that SS is limited by traps. We demonstrate improved TFET Ion performance by 1-2 orders of magnitude by scaling the equivalent oxide thickness from 2.7 to 1.5 nm. Furthermore, a novel benchmarking scheme is proposed to allow the comparison of different TFET data found in literature despite the different measurement conditions used.

Scalability of ultra-thin-body and BOX InGaAs MOSFETs on silicon

In this work, we show for the first time that VLSI-like gate-first self-aligned InGaAs MOSFETs on insulator on Si featuring raised source/drain (SID) can be fabricated at 300 nm pitch with gate lengths down to 24 nm. This is made possible thanks to the excellent thermal stability of ultra-thin-body and BOX InGaAs on insulator which can be used as a crystalline seed for III-V regrowth. The devices exhibit an excellent electrostatic integrity down to LG = 34 nm, comparable to the best reported tri-gate devices. We compare experimental device data to electrostatic simulations for bulk/on-insulator/tri-gate structures and extrapolate their ultimate scalability to very short LG.

Fabrication and analysis of vertical p-type InAs-Si nanowire Tunnel FETs

We report InAs-Si nanowire (NW) Tunnel FETs fabricated inside nanotube templates. High device yield and performances are obtained by optimizing the growth conditions and the fabrication flow using inorganic material as dielectric spacer, atomic-layer-deposition for the metal gate and by scaling the equivalent oxide thickness (EOT). We extract the exponential parameter B of Kanes tunneling model for direct bandgap (Eg) materials and compare it with experimental results. Moreover, studying the activation energy (EA) for TFETs with different EOTs allows us to distinguish the different conduction mechanisms.

Co-integrating high mobility channels for future CMOS, from substrate to circuits

Direct wafer bonding can be a vehicle for the dense co-integration of co-planar nano-scaled SiGe p-FETs and InGaAs n-FETs. Like for SiGe, direct wafer bonding enable the fabrication of fully depleted transistors having superior electrostatic control over the channel. Hybrid substrates can be also fabricated by direct wafer bonding with stacked ultra-thin high-mobility layers. A process flow allows fabricating n- and p-channel field effect transistors with ultra-thin body and BOX on the same wafer. Working CMOS inverters are obtained using a common front-end.

III/V layer growth on Si and Ge surfaces for direct wafer bonding as a path for hybrid CMOS

As Si-CMOS scaling has become increasingly challenging, III-V compound semiconductors such as InxGa1-xAs (x≥0.53) (InGaAs) are receiving much interest as channel material for nFET [1,2]. Together with SiGe as a pFET channel, they are considered as potential candidates to replace silicon for low power, high performance CMOS thanks to their better transport properties. A prerequisite in view of integration at VLSI scale is the formation of high quality III-V heterostructures on a silicon substrate to enable production on large size wafers.

Tri-gate In 0.53 Ga 0.47 As-on-insulator junctionless field effect transistors

A tri-gate In_0.53Ga_0.47As-on-insulator (InGaAs-OI) junctionless field-effect transistor (JLFET) architecture is demonstrated. The devices feature a 20-nm-thick n-In_0.53Ga_0.47As channel doped to 10¹⁸ /cm³ obtained by direct wafer bonding and a 3.5-nm-thick Al₂O₃ gate dielectric deposited by plasma-enhanced atomic layer deposition (PE-ALD). The impact of the fin width (W_fin) and gate length (L_g) scaling at fixed channel doping (N_d) and equivalent oxide thickness (EOT) on the device performance is discussed and benchmarked.

Hybrid III-V/SiGe technology: Improved n-FET performance and CMOS inverter characteristics

Recently, hybrid III-V/SiGe CMOS circuits have been demonstrated. Reported InGaAs n-FET performance was severely degraded by the CMOS flow compared to reference devices processed individually. We report on the recovered n-FET performance and its impact on CMOS inverters. In addition, we study the influence of back-bias on short-channel effects immunity and inverter transfer characteristics.