V. Djara

An InGaAs on Si platform for CMOS with 200 mm InGaAs-OI substrate, gate-first, replacement gate planar and FinFETs down to 120 nm contact pitch

We report on the first demonstration of ultra-thin body (50 nm), low defectivity 200 mm InGaAs-on-insulator (-OI) fabricated by direct wafer bonding technique (DWB) as well as a replacement gate process for self-aligned fully depleted InGaAs MOSFETs. These combined achievements highlight the viability of our approach for the VLSI integration of InGaAs at advanced nodes. Short channel replacement gate (RMG) and Gate-first (GF) FETs are reported for the first time using InGaAs-OI wafers with a 120nm contact-to-contact pitch. Record ION (118 μA/μm) at fixed operating voltage of 0.5V for InGaAs devices on Si is achieved on 50-nm-Lg RMG FinFETs. Both schemes feature highly scaled fins (down to 15 nm). Compared to a GF integration flow, RMG devices exhibit better Ion and DIBL characteristics. We also demonstrate FETs with 70 nm contacts and 120 nm pitch achieving high-ION.

Confined Epitaxial Lateral Overgrowth (CELO): A novel concept for scalable integration of CMOS-compatible InGaAs-on-insulator MOSFETs on large-area Si substrates

We report on the first demonstration of the CMOS-compatible integration of high-quality InGaAs on insulator (InGaAs-OI) on Si substrates by a novel concept named Confined Epitaxial Lateral Overgrowth (CELO). This method, based on selective epitaxy, only requires the use of standard large-area silicon substrates and typical CMOS processes. It enables the fabrication of InGaAs-OI starting from both bulk and SOI Si wafers. The InGaAs epitaxial structures are characterized by a very low defectivity, and can fulfill the requirements of both ultra-thin-body and fins-based advanced CMOS nodes. Gate-first self-aligned FinFETs (100-nm-long gate, 50-nm-wide fins and 250-nm-wide plug-contacts) with excellent electrical characteristics comparable to start-of-the-art InGaAs MOSFETs on Si are demonstrated, highlighting that this new concept has significant potential to enable introduction of high-mobility channel materials in high-volume manufacturing of advanced CMOS nodes.

Advanced 3D Monolithic hybrid CMOS with Sub-50 nm gate inverters featuring replacement metal gate (RMG)-InGaAs nFETs on SiGe-OI Fin pFETs

We demonstrate, for the first time, scaled hybrid inverters built in a 3D Monolithic (3DM) CMOS process featuring short-channel replacement metal gate (RMG) InGaAs-OI wide-fin/planar nFET top layer and SiGe-OI fin pFET bottom layer. We achieve state-of-the-art device integration, using raised source drain (RSD) on both levels and silicide on bottom pFETs. Bottom SiGe-OI pFETs are scaled down to sub-20 nm gate length (Lg) using a gate first (GF) flow, and top InGaAs nFETs scaled down to sub-50 nm Lg are fabricated using a RMG process. With an optimized thermal budget for the top InGaAs nFETs, we show that the 3D integration scheme does not degrade the performance of the bottom SiGe-OI pFETs. Finally, we demonstrate well-behaved integrated inverters with sub-50 nm Lg down to VDD = 0.25 V.

Three-dimensional monolithic integration of III–V and Si(Ge) FETs for hybrid CMOS and beyond

Three-dimensional (3D) monolithic integration can enable higher density and has the potential to stack independently optimized layers at transistor level. Owing to high mobility and lower processing temperatures, InGaAs is well-suited to be used as the top layer channel material in 3D monolithic integration along with Si/Si(Ge) FETs. A review of recent progress to develop InGaAs-on-Si(Ge) 3D Monolithic technology is presented here.

First demonstration of InGaAs/SiGe CMOS inverters and dense SRAM arrays on Si using selective epitaxy and standard FEOL processes

We report the first demonstration of InGaAs/SiGe CMOS inverters and dense SRAM arrays on Si, fabricated with InGaAs selective epitaxy and standard front end of line (FEOL) processes. This novel and scalable CMOS integration scheme enables InGaAs nFET fabrication in close proximity to SiGe pFETs (down to 25 nm spacing), resulting in 6T-SRAM arrays having a minimum cell size below 0.45 μm2. This scheme can be combined with any bulk Si or SOI-based planar or fin technology, and is compatible with standard large-area Si substrate. Individual InGaAs nFETs and SiGe pFETs are fabricated with a standard self-aligned CMOS-compatible process flow and feature LG scaled down to 35 nm. Moreover, the InGaAs nFET process flow includes selective epitaxy, raised source/drain (RSD) and high-k/metal gate (HKMG) modules. Finally, we report electrical characterization of isolated FETs and inverters as well as dense SRAM cells with planar and fin- FETs.

First RF characterization of InGaAs replacement metal gate (RMG) nFETs on SiGe-OI FinFETs fabricated by 3D monolithic integration

We report the first RF characterization of short-channel replacement metal gate (RMG) InGaAs-OI nFETs built in a 3D Monolithic (3DM) CMOS process. This process features RMG InGaAs-OI nFET top layer and SiGe-OI fin pFET bottom layer. We demonstrate state-of-the-art device integration on both levels. The bottom layer SiGe-OI pFETs are fabricated with a Gate-First (GF) process with fins scaled down to ∼15 nm width and featuring epitaxial raised source drain (RSD) and silicide. The top layer InGaAs nFETs are fabricated with a RMG process featuring a self-aligned epitaxial raised source drain (RSD). We show that the 3D monolithic integration scheme does not degrade the performance of the bottom SiGe-OI pFETs owing to an optimized thermal budget for the top InGaAs nFETs. From the RF characterizations performed (post-3D monolithic process) on multifinger-gate InGaAs-OI nFETs, we extract a cut-off frequency (Ft) of 16.4 GHz at a gate-length (Lg) of 120 nm. Measurements on various gate lengths shows increasing cut-off frequency with decreasing gate-length.

Volume and interface conduction in InGaAs junctionless transistors

Doped InGaAs were characterized using a revisited pseudo-MOSFET configuration. Two different conduction mechanisms were evidenced: volume and interface. The impact of film thickness, channel width and length is evaluated. Measurements at low temperatures complete the analysis.

Tri-gate In 0.53 Ga 0.47 As-on-insulator junctionless field effect transistors

A tri-gate In_0.53Ga_0.47As-on-insulator (InGaAs-OI) junctionless field-effect transistor (JLFET) architecture is demonstrated. The devices feature a 20-nm-thick n-In_0.53Ga_0.47As channel doped to 10¹⁸ /cm³ obtained by direct wafer bonding and a 3.5-nm-thick Al₂O₃ gate dielectric deposited by plasma-enhanced atomic layer deposition (PE-ALD). The impact of the fin width (W_fin) and gate length (L_g) scaling at fixed channel doping (N_d) and equivalent oxide thickness (EOT) on the device performance is discussed and benchmarked.

Hybrid InGaAs/SiGe CMOS circuits with 2D and 3D monolithic integration

Advanced CMOS nodes target high-performance at lower supply voltage. High-mobility III-V channel materials have the potential to meet this target. Although III-V materials such as InGaAs are beneficial for nFET channels, SiGe (or Ge) provides better hole mobility and is more suited for pFET channels. Therefore, a InGaAs/SiGe hybrid CMOS technology is being pursued for scaled nodes. There are significant challenges to cointegrate these two materials in a scalable process. In this regard, here, we present some of our recent work in InGaAs/SiGe CMOS integration through a novel direct epitaxy process for co-planar 2D integration. We also present our efforts in 3D monolithic integration of InGaAs-on-SiGe for CMOS and beyond.

Fabrication and characterization of InGaAs-on-insulator lateral N+/n/N+ structures

Lateral N+/n/N+ InGaAs-on-insulator structures are successfully fabricated by direct wafer bonding and selective regrowth. Electrical characterizations are performed for varying n-layer thickness from fully-depleted films up to the limit of partial depletion. Measurements under externally applied uniaxial tensile strain show an improved drive current.