Anyan Du

Enhanced performance in 50 nm N-MOSFETs with silicon-carbon source/drain regions

This paper reports a novel strained N-channel transistor structure with sub-100 nm gate lengths. The strained N-MOSFET features silicon-carbon (SiC) source and drain (S/D) regions formed by a Si recess etch and a selective epitaxy of SiC in the S/D regions. The carbon mole fraction incorporated is 1.3%. Lattice mismatch of /spl sim/0.65% between SiC and Si results in horizontal tensile strain and vertical compressive strain in the Si channel region, both contributing to substantial electron mobility enhancement. The conduction band offset /spl Delta/E/sub c/ between the SiC source and the strained-Si channel also contributes to increased electron injection velocity from the source. Implementation of the SiC stressors provides significant drive current I/sub DS/ enhancement in the N-MOSFETs. I/sub DS/ enhancement of 50% was observed for a gate length of 50 nm.

Lattice strain analysis of transistor structures with silicon–germanium and silicon–carbon source∕drain stressors

We report the characterization of strain components in transistor structures with silicon–germanium (Si0.75Ge0.25) and silicon–carbon (Si0.99C0.01) stressors grown by selective epitaxy in the source and drain regions. The spacing between the source and drain stressors is 35nm. Lattice strain analysis was performed using high-resolution transmission electron microscopy (HRTEM) and diffractograms obtained by fast Fourier transform of HRTEM images. The lateral strain component exx and the vertical strain component ezz were derived from the (220) and (002) reflections in the diffractogram, respectively. SiGe source and drain stressors lead to lateral compressive strain and vertical tensile strain in the Si channel. On the other hand, the SiC source and drain stressors give rise to lateral tensile strain and vertical compressive strain in the Si channel, an effect complementary to that of SiGe source∕drain stressors. The results of this work will be useful for channel strain engineering in complementary metal-...

Strained N-Channel FinFETs with 25 nm Gate Length and Silicon-Carbon Source/Drain Regions for Performance Enhancement

We report the demonstration of 25 nm gate length L_G tri-gate FinFETs with Si_0.99C_0.01 source and drain (S/D) regions. The strain-induced mobility enhancement due to the Si_0.99C_0.01 S/D leads to a drive current I_Dsat improvement of 20% at a fixed off-state current I_off of 1times10^-7 A/mum. With additional channel strain engineering, FinFETs incorporating Si_0.99C_0.01 S/D and a tensile-stress silicon nitride (SiN) capping etch-stop layer (ESL) achieve an I_Dsat enhancement of 56%

Thermally robust high quality HfN/HfO/sub 2/ gate stack for advanced CMOS devices

We report for the first time a thermally stable and high quality HfN/HfO/sub 2/ gate stack for advanced CMOS applications. Due to the superior oxygen diffusion barrier of HfN as well as the thermal stability of the HfN/HfO/sub 2/ interface, the EOT of the HfN/HfO/sub 2/ gate stack has been successfully scaled down to less than 10/spl Aring/ with excellent leakage, boron penetration immunity, and long-term reliability, even after 1000/spl deg/C RTA treatment for 20 s, without using surface nitridation prior to HfO/sub 2/ deposition. The mobility is improved significantly for devices without surface nitridation. Negligible change in both EOT and the work function of the HfN/HfO/sub 2/ gate stack are observed after 1000/spl deg/C RTA.

50 nm Silicon-On-Insulator N-MOSFET Featuring Multiple Stressors: Silicon-Carbon Source/Drain Regions and Tensile Stress Silicon Nitride Liner

A novel n-channel strained SOI transistor featuring silicon-carbon (SiC) source/drain (S/D) regions and tensile stress silicon nitride (SiN) liner is demonstrated for the first time. Drive current IDsat enhancement contributed by the dual stressors is found to be additive and a significant increase in IDsat of 55% is observed at a gate length LG of 50 nm. In addition, we report the dependence of drive current on channel orientation, with highest I Dsat observed for strained n-MOSFETs with the |010| channel direction. A study of the carrier transport characteristics indicate reduced channel back-scattering and enhanced carrier injection velocity due to the strain effects

Effect of germanium concentration and tunnel oxide thickness on nanocrystal formation and charge storage/retention characteristics of a trilayer memory structure

The effect of germanium concentration and the rapid thermal oxide (RTO) layer thickness on the nanocrystal formation and charge storage/retention capability of a trilayer metal–insulator–semiconductor device was studied. We found that the RTO and the capping oxide layers were not totally effective in confining the Ge nanocrystals in the middle layer when a pure Ge middle layer was used for the formation of nanocrystals. From the transmission electron microscopy and secondary ion mass spectroscopy results, a significant diffusion of Ge atoms through the RTO and into the silicon substrate was observed when the RTO layer thickness was reduced to 2.5 nm. This resulted in no (or very few) nanocrystals formed in the system. For devices with a Ge+SiO2 cosputtered middle layer (i.e., lower Ge concentration), even though a higher charge storage capability was obtained from devices with a thinner RTO layer, the charge retention capability was poorer as compared to devices with a thicker RTO layer.

Work-Function Tuning of TaN by High-Temperature Metal Intermixing Technique for Gate-First CMOS Process

This letter investigates the feasibility of adjusting the work function (WF) of TaN metal gate by intermixing (InM) of ultra-thin TaN/Metal stacks at high temperature. This could be useful for the integration of dual-WF metal gates in a gate-first CMOS process without exposing gate dielectric during metal-etching process. TaN/Tb and TaN/Ir stacks were studied, and it is found that the WF of TaN can be readily modulated through metal InM in TaN/Tb stack after high-temperature treatment (~1000 degC), which simulates the source/drain dopant activation process in a gate-first CMOS process. Factors affecting the InM process will be discussed. Successful transistor threshold voltage adjustment by ~300 mV on high-kappa HfTaON/HfO2 dielectrics has also been demonstrated in TaN/Tb stack using this technique

High performance ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate MIM capacitors for RF and mixed signal IC applications

In this paper, a high performance ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate metal-insulator-metal (MIM) capacitor is demonstrated for the first time with high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz to 20 GHz, low leakage current of 7.45/spl times/10/sup -9/ A/cm/sup 2/ at 2 V, low VCC (voltage coefficients of capacitance), and excellent reliability. The superior electrical properties and reliability suggest that the ALD HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising material for MIM capacitors for Si RF and mixed signal IC applications.

A Correlation Study of Thermal Stability on Porous Low k

The thermal stability of organic porous low k, porous SiLK with a dielectric constant of 2.4, has been studied. Organic low k material SiLK TM , non-porous SiLK, with a dielectric constant 2.8 is used as a baseline for comparison. Each sample was subjected to annealing cycles, where each cycle was conducted in a vertical furnace for one hour in an N 2 ambient. The annealing temperature was set at either 430°C or 450°C. After every alternate cycle, the film properties were measured and compared to the unannealed sample for changes in film shrinkage, refractive index, dielectric constant, roughness, breakdown voltage, pore size, hardness and Youngs modulus. Changes in film properties were investigated and evaluated by using opti-probe, FTIR, XPS, AFM, mercury probe, nano-indentation, SEM and TEM techniques.

Strained Silicon–Germanium-on-Insulator n-Channel Transistor with Silicon Source and Drain Regions for Performance Enhancement

We report the incorporation of lattice-mismatched source/drain (S/D) stressors for the formation of strained SiGe n-channel transistors with gate lengths LG down to 70 nm. The strained SiGe channel transistor features silicon S/D regions which are pseudomorphically grown by selective epitaxy. Lattice mismatch between the silicon S/D region and the SiGe channel was exploited to induce lateral tensile strain and vertical compressive strain in the channel, leading to enhancement in electron mobility. Experimental results on the strained SiGe n-channel transistors correlate well with stress simulations. Control devices with the lattice-matched SiGe S/D were also fabricated. At a gate length of 70 nm, the tensile strained-SiGe channel n-FET with Si S/D demonstrates 36% higher linear drain current and 20% higher saturation drive current over the control device.