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Dive into the research topics where F. Monsieur is active.

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Featured researches published by F. Monsieur.


international reliability physics symposium | 2003

Evidence for hydrogen-related defects during NBTl stress in p-MOSFETs

V. Huard; F. Monsieur; G. Ribes; S. Bruyere

This work gives an insight into the degradation mechanisms during a negative bias instability stress on ultrathin oxides (t/sub ox/=20 /spl Aring/). The generation of interface traps and oxide defects is shown to impact parameters such as the threshold voltage. Their generation is linked to the release of hydrogen species at the interface according to the hydrogen release model. Only hot holes can be trapped by the anode hole injection phenomenon.


international electron devices meeting | 2011

Fundamental aspects of HfO 2 -based high-k metal gate stack reliability and implications on t inv -scaling

E. Cartier; A. Kerber; Takashi Ando; Martin M. Frank; Kisik Choi; Siddarth A. Krishnan; Barry P. Linder; Kai Zhao; F. Monsieur; James H. Stathis; Vijay Narayanan

Experimental reliability trends indicate that tinv-scaling with HKMG stacks remains challenging because NBTI, PBTI and TDDB reliability margins rapidly decrease with decreasing tinv values and increasing gate leakage current. A case is made that these observed trends arise from the layer structure and the materials properties of the SiO(N)/HfO2 dual dielectric. Therefore, fundamental reliability limitations appear to increasingly impact HKMG stack scaling.


international electron devices meeting | 2012

UTBB FDSOI transistors with dual STI for a multi-V t strategy at 20nm node and below

L. Grenouillet; M. Vinet; J. Gimbert; B. Giraud; J. P. Noël; Qing Liu; Prasanna Khare; M. A. Jaud; Y. Le Tiec; Romain Wacquez; T. Levin; P. Rivallin; Steven J. Holmes; S. Liu; K. J. Chen; O. Rozeau; P. Scheiblin; E. McLellan; M. Malley; J. Guilford; A. Upham; Richard Johnson; M. Hargrove; Terence B. Hook; Stefan Schmitz; Sanjay Mehta; J. Kuss; Nicolas Loubet; S. Teehan; M. Terrizzi

We introduce an innovative dual-depth shallow trench isolation (dual STI) scheme for Ultra Thin Body and BOX (UTBB) FDSOI architecture. Since in the dual STI configuration wells are isolated from one another by the deepest trenches, this architecture enables a full use of the back bias while staying compatible with both standard bulk design and conventional SOI substrates. We demonstrate in 20nm ground rules that we are able to tune Vt by more than 400mV, that transistor performance can be boosted by up to 30% and that Ioff can be controlled over 3 decades by allowing more than VDD/2 to be applied on the back gate.


Microelectronics Reliability | 2001

Wear-out, breakdown occurrence and failure detection in 18–25 Å ultrathin oxides

F. Monsieur; E. Vincent; G. Pananakakis; G. Ghibaudo

Abstract In this paper, a comprehensive description of the ultrathin oxide failure evolution is presented. For sub-25 A, Hard BD is no longer hard. A complete description of the novel failure manifestation (progressive breakdown) is done. Associated wear-out is modelled and a physical mechanism is proposed. Finally, the relevance of the failure definition is discussed. It is a crucial point, to adopt a rigorous methodology for reliability prediction. It is concluded that, in the case of progressive breakdown, noise occurrence must be considered as the relevant time to failure.


international electron devices meeting | 2008

High voltage devices integration into advanced CMOS technologies

Raul Andres Bianchi; F. Monsieur; Floria Blanchet; C. Raynaud; Olivier Noblanc

This paper focuses on CMOS technologies for mobile applications having integrated high voltage devices to address analog baseband and RF power applications. Technology evolution from BCD-like to advanced CMOS technologies on bulk and thin SOI substrates and some selected device architectures (extended drain MOSFET, drift MOSFET, lateral and vertical diffused MOSFET) are reviewed. Main challenges encountered when integrating these devices in advanced CMOS are explained. The influence of the gate oxide thickness on the relevant figures of merit and some considerations on performance-reliability trade-off are provided.


custom integrated circuits conference | 2009

High voltage devices in advanced CMOS technologies

Raul Andres Bianchi; C. Raynaud; Floria Blanchet; F. Monsieur; Olivier Noblanc

CMOS technologies for mobile systems require integrated high voltage devices to address analog baseband and RF power applications. Technology and device architecture evolution, from 0.5μm BCD-like to advanced 45nm CMOS, on bulk and thin SOI substrates, are reviewed in this paper. Main challenges encountered when integrating these devices in advanced CMOS are explained. The influence of the gate oxide thickness on the relevant figures of merit and some considerations on performance-reliability trade-off are provided.


Microelectronics Reliability | 2005

Multi-vibrational hydrogen release: Physical origin of Tbd,Qbd power-law voltage dependence of oxide breakdown in ultra-thin gate oxides

G. Ribes; S. Bruyere; M. Denais; F. Monsieur; V. Huard; D. Roy; G. Ghibaudo

Abstract In this work we report an experimental observation of the current dependence on the defect generation probability driving to breakdown. We propose the MVHR model (multi-vibrational hydrogen release) based on the multi-vibrational excitation of the Si–H bond stretching mode. By this way we explain the power-law dependence of charge and time to breakdown and highlight its limit on PMOS inversion.


international integrated reliability workshop | 2002

Evidence for defect-generation-driven wear-out of breakdown conduction path in ultra thin oxides

F. Monsieur; E. Vincent; G. Ribes; V. Huard; S. Bruyere; D. Roy; G. Pananakakis; G. Ghibaudo

This paper considers the physical mechanisms responsible for the progressive (i.e. smooth or noisy) breakdown manifestation commonly measured on ultra-thin oxides (Tox<25 /spl Aring/). First, it is verified that the theory previously published is relevant by highlighting progressive behavior predicted on thicker oxides (50 /spl Aring/). Second, the stored energy is shown not to be correlated to the progressive behavior even if it influences the failure and its occurrence. At last, the progressiveness being gate voltage and temperature driven, it is stated that the defect generation probability drives the breakdown degradation after its creation. This is proven by measuring the influence on the progressiveness of a bulk bias applied during the stress of a pMOS in the inversion regime.


international reliability physics symposium | 2010

High-K gate stack breakdown statistics modeled by correlated interfacial layer and high-k breakdown path

G. Ribes; P. Mora; F. Monsieur; M. Rafik; Fernando Guarin; G. Yang; D. Roy; W.L. Chang; James H. Stathis

We show that a model in which the breakdown of the interfacial layer induces a correlated breakdown in the high-K, at the same location, provides a good model of the high-K/IL gate stack statistics. We discuss of the implication of this model on the lifetime projection.


international integrated reliability workshop | 2001

Time to breakdown and voltage to breakdown modeling for ultra-thin oxides (Tox<32/spl Aring/)

F. Monsieur; E. Vincent; D. Roy; S. Bruyre; G. Pananakakis; G. Ghibaudo

This paper presents reliability results related to ultra-thin oxides (20/spl Aring/< Tox < 32/spl Aring/). First of all Voltage to Breakdown (Vbd) is evidenced to linearly depend on the oxide thickness. Moreover, its acceleration factor is found independent of temperature and oxide thickness. Consequently, an empirical model is proposed for the voltage to breakdown dependencies. This model can be transposed to the time to breakdown (Tbd) analysis and a good agreement is found for Tbd prediction and experimental observations. Relationship to other literature models is also discussed.

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