G. Ribes

Review on high-k dielectrics reliability issues

High-k gate dielectrics, particularly Hf-based materials, are likely to be implemented in CMOS advanced technologies. One of the important challenges in integrating these materials is to achieve lifetimes equal or better than their SiO/sub 2/ counterparts. In this paper we review the status of reliability studies of high-k gate dielectrics and try to illustrate it with experimental results. High-k materials show novel reliability phenomena related to the asymmetric gate band structure and the presence of fast and reversible charge. Reliability of high-k structures is influenced both by the interfacial layer as well as the high-k layer. One of the main issues is to understand these new mechanisms in order to asses the lifetime accurately and reduce them.

Interface trap generation and hole trapping under NBTI and PBTI in advanced CMOS technology with a 2-nm gate oxide

This paper gives an insight into the degradation mechanisms during negative and positive bias temperature instabilities in advanced CMOS technology with a 2-nm gate oxide. We focus on generated interface traps and oxide traps to distinguish their dependencies and effects on usual transistor parameters. negative bias temperature instability (NBTI) and positive bias temperature instability in both NMOS and PMOS have been compared and a possible explanation for all configurations has been suggested. Recovery and temperature effect under NBTI were also investigated showing different behaviors of the two components.

Evidence for hydrogen-related defects during NBTl stress in p-MOSFETs

This work gives an insight into the degradation mechanisms during a negative bias instability stress on ultrathin oxides (t/sub ox/=20 /spl Aring/). The generation of interface traps and oxide defects is shown to impact parameters such as the threshold voltage. Their generation is linked to the release of hydrogen species at the interface according to the hydrogen release model. Only hot holes can be trapped by the anode hole injection phenomenon.

Paradigm Shift for NBTI Characterization in Ultra-Scaled CMOS Technologies

We have proposed a new methodology to study both DC and AC NBTI effects taking into account both the recoverable property of the degradation and the electrical parameter legitimacy in each electrical configuration. In this new framework, characterization phases induce no effect (neither recovery nor extra-damage) on the degradation. For DC NBTI with a partial/uniform recovery, a generalized universal recovery modelling has been proposed for the first time to estimate the recovery amount. This modelling is particularly useful to calculate the recovery time needed after a stress period to reach a (decrease) degradation amount. For AC NBTI case, NBTI has been directly studied on circuits parameters opening new promising perspectives in term of reliability criteria

Designing in reliability in advanced CMOS technologies

Assessment of design implications due to degradation of CMOS devices is increasingly required in the latest technologies. This paper presents selected topics relevant to realize an efficient design-in reliability methodology in the latest generation CMOS technologies. NBTI is discussed in terms of characterization using On-The-Fly (OTF) methodology. Extension of OTF method is discussed using bias patterns to gain insights into NBTI under analog operation. A reliability simulation methodology is discussed against requirements for optimization and integration within an existing design flow. The features of this methodology are illustrated using some simple design examples.

Impact of TiN Metal gate on NBTI assessed by interface states and fast transient effect characterization

With the decrease of the high-k layer thickness, NBTI becomes more critical than PBTI. The relative contribution of interface states and trapping on NBTI is analysed in Hf-based stacks. Dit density and generation kinetics were found to be similar to that in SiO2, whereas a very large fast trapping component was evidenced. The pre-existing traps responsible for this fast trapping effect were related to N incorporation in the interfacial layer after TiN PVD deposition. Finally, a significant lifetime improvement is achieved using TaC as gate material.

Evidence for defect-generation-driven wear-out of breakdown conduction path in ultra thin oxides

This paper considers the physical mechanisms responsible for the progressive (i.e. smooth or noisy) breakdown manifestation commonly measured on ultra-thin oxides (Tox<25 /spl Aring/). First, it is verified that the theory previously published is relevant by highlighting progressive behavior predicted on thicker oxides (50 /spl Aring/). Second, the power dissipated is shown not to be correlated to the progressive behavior even if it influences the failure and its occurrence. Finally, the progression being gate voltage and temperature driven, it is shown that the defect generation probability drives the breakdown degradation after its creation. This is proven by measuring the influence on the progression of a bulk bias applied during the stress of a pMOS device in the inversion regime.

New perspectives on NBTI in advanced technologies: modelling & characterization

This work presents new perspectives of the NBTI in advanced technology. Both modelling and characterization of NBTI are investigated for the maturation of the reliability management in advanced node technologies. A physical-based VT instability model is presented considering interface trapped charges, fixed charges and oxide trapped holes effects. Finally, we discuss on the lifetime concept in the case of recoverable NBTI-induced degradation.

Multi-vibrational hydrogen release: Physical origin of Tbd,Qbd power-law voltage dependence of oxide breakdown in ultra-thin gate oxides

Abstract In this work we report an experimental observation of the current dependence on the defect generation probability driving to breakdown. We propose the MVHR model (multi-vibrational hydrogen release) based on the multi-vibrational excitation of the Si–H bond stretching mode. By this way we explain the power-law dependence of charge and time to breakdown and highlight its limit on PMOS inversion.

New methodologies of NBTI characterization eliminating recovery effects

This work gives new insights of negative bias temperature instability (NBTI) characterization methodologies in advanced CMOS technology. NBTI is well-known to seriously limit the circuit performances in p-channel MOSFETs, in relation to both interface trap generation and hole trapping in the gate oxide. Hole detrapping from oxide traps during electrical parameter extractions, also called a recovery phenomenon, is unanimously acknowledged to be the most critical phenomenon avoiding a proper characterization of the effective damage. We point out here new NBTI evaluation techniques using pulsed voltages on the gate and on the drain to characterize NBT degradation and quantify recovery effects in the usual methodology.