Vaclav Simek

GPU Acceleration of 2D-DWT Image Compression in MATLAB with CUDA

This article presents the details about the acceleration of 2D wavelet-based medical data (image) compression on MATLAB with CUDA. It is obvious that the diagnostic materials (mostly as acertain type of image) are increasingly acquired in a digital format. Therefore, common need to daily manipulate huge amount of data brought about the issue of compression within a very less stipulated amount of time. Attention is given to the acceleration processing flow which exploits the massive parallel computational power offered by the latest NVIDIA graphics processor unit (GPU). It brings a compute device that can be programmed using a C-like language using CUDA, (compute unified device architecture). In the same time, a number of attractive features can be exploited for a broad class of intensive data parallel computation tasks. The final part of discussion outlines possible directions towards future improvements of compression ratio and processing speed.

Towards Accelerated Computation of Atmospheric Equations Using CUDA

Main objective of this paper is to outline possibleways how to achieve a substantial acceleration in caseof advection-diffusion equation (A-DE) calculation,which is commonly used for a description of thepollutant behavior in atmosphere. A-DE is a kind ofpartial differential equation (PDE) and in general caseit is usually solved by numerical integration due to itshigh complexity. These types of calculations are timeconsuming thus the main idea of our work is to adoptCUDA platform and commodity GPU card to do thecalculations in a faster way. The solution is based onmethod of lines with 4th order Runge-Kutta scheme tohandle the integration. As a matter of fact, the selectedapproach involves number of auxiliary variables andthus the memory management is critical in order toachieve desired performance. We have implementedseveral possible solutions that use different memoryaccess schemes. Detailed evaluation is provided in thispaper where the obtained results show a tremendousprocessing speed up in comparison to CPU.

Implementing A Unique Chip Id On A Reconfigurable Polymorphic Circuit

A unique unclonable chip ID has been implemented using various platforms in the recent years. In this paper, we investigate the use of polymorphic gates as a new mechanism for implementing a unique chip ID in systems already containing some polymorphic gates. The proposed solution exploits the fact that switching time of polymorphic gates (controlled by V dd ) is slightly different even for neighboring gates on the same die because of fabrication variations. We applied a partial reconfiguration in order to generate 48-bit IDs on the reconfigurable polymorphic REPOMO32 chip that we have developed in our previous research. We achieved 94.44% stable bits which is reasonably close to existing approaches. DOI: http://dx.doi.org/10.5755/j01.itc.42.1.925

Chip Temperature Selfregulation for Digital Circuits Using Polymorphic Electronics Principles

The paper presents a new design approach to digital circuits that provides for an increased chip operation reliability from temperature point of view. The key aspect behind the proposed method of approach is to avoid chip overheating due to special design and subsequent integration of dedicated circuit controller. Such element is blended seamlessly with the surrounding circuitry and posses the ability to reconfigure itself when the temperature of the chip goes beyond defined temperature boundary. After the end of reconfiguration phase, the controller ensures only indispensable function. By this arrangement, the power and heat dissipation of the circuit is reduced until the chip temperature falls again under certain level. When the chip is cooled down appropriately, the controller returns back to normal operating mode automatically. The proposed approach utilises principles of polymorphic digital circuits which embrace smart and fast reconfiguration, compact and cost-effective design with embedded sensors, where the aim is to ensure overall system stability and in the same time increase its dependability.

On analysis of fabricated polymorphic circuits

The paper describes a reconfigurable polymorphic chip REPOMO32, experiments carried out with this chip and provides report on important experiences with regard to practical applications of digital polymorphic circuits sensitive to the power supply voltage (Vdd). REPOMO32 contains array of 32 configurable logic elements which can perform polymorphic NAND/NOR function controlled by the level of the Vdd. Moreover, it can be declared as the first fabricated chip of this kind which basically allows the user to design more complex circuits than only a few gates.

Behavior of CMOS polymorphic circuits in high temperature environment

The paper describes a series of experiments performed with the aim to analyze the fundamental impact of high temperatures on behavior of polymorphic digital circuits. These experiments were conducted using a reconfigurable polymorphic chip REPOMO32 which is configured (in addition to the configuration bit stream) using the level of power supply voltage (Vdd). Experiments show that polymorphic gates in the chip can be easily involved (in terms of functionality) not only by Vdd, but also by temperature. Because experiments also prove that the physical design of the REPOMO32 chip is robust enough to keep the functionality of all circuitry of the REPOMO32 and its dynamic parameters are stable enough under wide range of operating temperature, the chip can also be used for future designs of digital polymorphic circuits controlled by temperature.

GPU Accelerated Solver of Time-Dependent Air Pollutant Transport Equations

Main objective of this paper is to outline possible ways how to achieve a substantial acceleration in case of advection-diffusion equation (A-DE) calculation, which is commonly used for a description of the pollutant behavior in atmosphere. A-DE is a kind of partial differential equation (PDE) and in general case it is usually solved by numerical integration due to its high complexity. These types of calculations are time consuming thus the main idea of our work is to adopt compute unified device architecture (CUDA) software framework and commodity add-on card with generalpurpose graphics processing unit (GPU) to do the calculations in a faster way. The solution is based on method of lines with 4 th order Runge-Kutta scheme to handle the integration. As a matter of fact, the selected approach involves number of auxiliary variables and thus the memory management is critical in order to achieve desired performance. From a technical point of view, we have implemented a particular variant of the A-DE system, where the pollutant concentration is time-dependent. An efficient data handling is primarily based on the exploitation of shared memory blocks and texture caches inside GPU chip. Detailed evaluation of the obtained results is given in this paper where an astonishing execution speed up of GPU-based solution is demonstrated in comparison to standard CPU.

Synthesis Methodology of Polymorphic Circuits Using Polymorphic NAND/NOR Gates

In this paper, a novel approach dealing with the issues of multifunctional (polymorphic) logic circuits synthesis is presented. Crucial notion behind the polymorphic concept resides in the fact that such kind of circuit is able to perform more than one logic function, while the underlying structure keeps its arrangement untouched. The outlined behaviour is established by means of utilizing special multifunctional components (gates) during circuit design phase, where the individual connections among them remains unchanged (no reconfiguration takes place). The exact function, which the circuit is purposely executing at a given moment, is determined by the actual operating environment (e.g. supply voltage, temperature or a special signal). The proposed synthesis method is based on a formal Boolean representation of corresponding functions. Its main advantage can be recognized in strictly rigid and algorithmic notation with the employment of minimization techniques, which is in a direct contrast to competitive solutions, predominantly based on heuristic approaches.

Reconfigurable Platform with Polymorphic Digital Gates and Partial Reconfiguration Feature

Nowadays, there can be identified at ease a number of significant areas based on a conventional digital circuitry, such as evolvable or adaptive hardware, fault-tolerant architectures, reconfigurable systems or circuit development, where the introduction of partial reconfiguration principles may bring significant benefits with respect to traditional approaches. In case of polymorphic digital circuits (polymorphic digital circuit is able to perform more than one intended function, it typically has one stable structure for all required functions and the actually performed function or mode depends on a state of an environment) only one small-scale solution has been reported so far - the REPOMO. In this paper, main attention is given to the proposal of an innovative approach with increased flexibility, where the resulting capabilities are demonstrated.

Synthesis tool for design of complex polymorphic circuits

This paper is dealing with research activities carried out in the domain of unconventional, polymorphic electronics. Main attention is focused on the logic synthesis aspects of complex polymorphic circuits. The introductory part elucidates a fundamental concept of polymorphic electronics and highlights its important properties. In addition, substantial advantages of this paradigm in comparison to conventional circuit design approach are discussed together with an identification of possible shortcomings. Main contribution of this paper is the proposal and implementation of a synthesis technique which makes it feasible to achieve an area-efficient results in case of complex polymorphic circuit involving hundreds of gates. Finally, accomplished experimental results and their analysis is provided.