Vaibhav Karkare

A 130-

Spike sorting is an important processing step in various neuroscientific and clinical studies. Energy-efficient spike-sorting ASICs are necessary to allow real-time processing of multi-channel, wireless neural recordings. Spike-sorting ASICs have to meet stringent power-density constraints and must provide significant data-rate reduction for wireless transmission. Most existing designs either provide only spike detection for multi-channel processing, or they provide detection and feature extraction only for a single channel. In this paper, we demonstrate the design of a spike-sorting DSP chip that can perform detection, alignment, and feature extraction simultaneously for 64 channels. Spike-sorting algorithms chosen based on a complexity-performance analysis were implemented on ASIC using a MATLAB/Simulink-based architecture design framework. Energy-delay tradeoffs of the design were analyzed to identify the optimal degree of interleaving. The chip was implemented with a modular architecture, and can be configured to process 16, 32, 48, or 64 channels. Inactive cores are power-gated when the chip is operated to process a reduced number of channels. The chip, implemented in a 90-nm CMOS process, has a power dissipation of 130 μW (power density of 30 μW/mm2) when processing all 64 channels and provides a data-rate reduction of 91.25% (11.71 Mb/s to 1.02 Mb/s).

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Energy-efficient spike-sorting DSPs are necessary to allow for the real-time processing of multi-channel, wireless, implantable neural recordings. Online, unsupervised clustering forms an integral part of on-chip spike sorting. However, previous spike-sorting DSPs did not include unsupervised clustering due to the large memory required for its implementation. We demonstrate the first multi-channel spike-sorting DSP chip that includes online, unsupervised clustering. On-chip clustering has been made possible by using a two-stage implementation of an online clustering algorithm, a noise-tolerant distance metric, and selectively clocked high-VT register banks. The 16-channel spike-sorting chip, implemented in a 65-nm CMOS process, has a power dissipation of 75 μW at a supply voltage of 270 mV. The implementation of on-chip clustering provides a 240× reduction in the output data rate, which is 3× higher than the data-rate reduction obtained from previous spike-sorting DSP chips.We describe a neural spike-sorting processor that provides unsupervised clustering simultaneously for 16 channels. The use of a two-stage clustering algorithm, noise-tolerant distance metric, and selectively clocked high-VT register arrays makes online clustering feasible for implementation. The spike-sorting processor has a power consumption of 75µW at 270mV and an area of 2.45mm2 in a 65nm CMOS.

W, 64-Channel Neural Spike-Sorting DSP Chip

This paper shows that due to their negligibly low leakage, in certain applications, chips utilizing power gates built even with todays relatively large, high-voltage micro-electro-mechanical (MEM) relays can achieve lower total energy than those built with CMOS transistors. A simple analysis provides design guidelines for off-time and savings estimates as a function of technology parameters, and quantifies the further benefits of scaled relay designs. Finally, we demonstrate a relay chip successfully power-gating a CMOS chip, and show a relay-based timer suitable for self-timed operation.

A 75-µW, 16-Channel Neural Spike-Sorting Processor With Unsupervised Clustering

Spike sorting is an important processing step in various neuroscientific and clinical studies. An on-chip spike-sorting DSP must provide data-rate reduction while maintaining a power density much less than 800 μW/mm2. Most existing designs either provide only spike detection for multi-channel processing, or they provide detection and feature extraction only for a single channel. We demonstrate a chip for detection, alignment, and feature extraction simultaneously for 64 channels. Spike-sorting algorithms identified from a complexity-performance analysis are implemented on ASIC using a Matlab/Simulink-based architecture design framework. The chip has a modular architecture, which allows it to be configured to process 16, 32, 48, or 64 channels. Inactive cores are power-gated to reduce power consumption when the chip operates for less than 64 channels. The chip is implemented in a 90-nm CMOS process and has a power dissipation of 130 μW (power density of 30 μW/mm2) when processing all 64 channels. A data-rate reduction of 91.25% (11.71 Mbps to 1.02 Mbps) is achieved.

Analysis and demonstration of MEM-relay power gating

Many applications in science and medicine that use neurophysiology require on-chip spike detection. Since implantable electronics have strict requirements on area and power, spike detection must be as power- and area-efficient as possible. In this paper, we examine whether analog or digital spike detection is more efficient. The motivation behind an analog implementation for detection is to save the power spent to quantize the input samples, which has an exponential dependence on the bit resolution. From our analysis using 90-nm technology, we find that digital implementations are more efficient for lower resolutions (up to 8 or 9 bits), whereas analog implementations are more power-efficient for higher resolutions. This conclusion is found to be valid across a wide range of SNRs and neuronal firing rates.

A 130-μW, 64-channel spike-sorting DSP chip

Wireless sensing of electrophysiological signals in day-to-day life will enable various clinical, research, and wellness applications. This paper reviews the design requirements of biosignal recording interfaces for use in remote, unconstrained environments and put the performance achieved by state-of-the-art designs in perspective. In particular, we emphasize the need for biosignal recording front-ends to provide a dynamic range of approximately 100 dB, while meeting an input-referred noise level of a few μVrms. It is difficult to achieve a low input-referred noise and a high dynamic range using conventional voltage-domain amplifiers; state-of-the-art designs provide only ~60 dB of dynamic range. We propose to process electrophysiological signals in the phase domain, since there is no physical bound on phase. Low-noise VCO-based front-ends can be designed to extend the dynamic range by 40dB without paying a significant power, noise, or area penalty compared to state-of-the-art biosignal recording front-ends. For high-channel-count action-potential recording systems the system power is dominated by the transmitter if raw data is transmitted. In spite of the power reduction achieved by innovative biomedical transmitter designs, on-chip processing becomes necessary to reduce the output data rate for many-channel recording systems. It is important for neuroscientists and electrical engineers to agree upon a scheme to reduce the output data rate. We enlist and discuss a few data-rate reduction options for action-potential recordings. In addition, it is also desirable to make the biosignal sensors self-powered, thus avoiding the need for battery replacement/recharging. We briefly review existing energy-harvesting techniques and discuss future directions.

An efficiency comparison of analog and digital spike detection

This chapter discusses algorithm, architecture, and circuit techniques for efficient implementation of neural signal processing circuits. In particular, the focus is on spike sorting and compressive sampling for action potentials. The chapter begins with an introduction to spike sorting and compressive sampling, and the need for their implementation in modern-day neural recording systems. We then illustrate, through examples, some useful methods for algorithm selection and optimization. Digital design techniques that are beneficial in power and area reduction for neural signal processing DSPs are also discussed. Finally, we discuss the challenges and future directions in the area of biosignal processing.

Robust, reconfigurable, and power-efficient biosignal recording systems

This chapter presents a design example of a kHz-rate neural processor. A brief introduction to kHz design will be provided, followed by an introduction to neural spike sorting. Several spike-sorting algorithms will be reviewed. Lastly, the design of a 130-μW, 64- channel spike-sorting DSP chip will be presented.

Energy-Efficient Digital Processing for Neural Action Potentials

In this chapter we will discuss the methods for time frequency analysis and the DSP architectures for implementing these methods. In particular, we will use the FFT and the wavelet transform as our examples for this chapter. The well-known Fast Fourier Transform (FFT) is applicable to the frequency analysis of stationary signals. Wavelets provide a flexible time-frequency grid to analyze signals whose spectral content changes over time.