Valentin Tihhomirov

A scalable model based RTL framework zamiaCAD for static analysis

As of today, RTL still remains the primary abstraction level for VLSI SoC design entry and state-of-the-art design flows need to cope with designs of enormous size, and thus, to scale well. This paper presents an open-source framework zamiaCAD based on a scalable model that includes both, a comprehensive elaboration front-end for RTL design and design processing back-end flows. The persistence and scalability are guaranteed by a custom-designed and highly optimized object database. As an HDL-centric framework it follows the concept of non-intrusiveness. In this paper, we discuss in detail the concepts of design elaboration into the scalable design model and present an evaluation of the model for static analysis as one of the back-end applications. Experimental results on very large designs show that zamiaCAD compares favorable to other frameworks with respect to the scalability aspects.

FPGA based fault emulation of synchronous sequential circuits

This paper describes a feasibility study of accelerating fault simulation by emulation on FPGA. Fault simulation b an important subtask in test pattern generation and it is frequently used throughout the test generation process. In order to further speed up simulation, we propose to make use of reconfigurable hardware by emulating circuit together with fault insertion structures on FPGA. Experiments showed that it is beneficial to use emulation for circuits/methods that require large numbers of test vectors, e.g., sequential circuits and/or genetic algorithms.

Rejuvenation of nanoscale logic at NBTI-critical paths using evolutionary TPG

One of the main reliability concerns in the nanoscale logic is the time-dependent variation caused by Negative Bias Temperature Instability (NBTI). It increases the threshold voltage of pMOS transistors, which slows down signal propagation along the paths between flip-flops. As a consequence, NBTI may cause transient faults and, ultimately, permanent circuit functional failure. In this paper, we propose an innovative NBTI mitigation approach by rejuvenation of nanoscale logic along NBTI-critical paths. The method is based on hierarchical NBTI-critical paths identification and rejuvenation stimuli generation using an Evolutionary Algorithm. The rejuvenation stimuli are used to drive to the recovery phase the pMOS transistors that are the most significant for the NBTI-induced path delay. This rejuvenation procedure is to be applied to the circuit as an execution overhead at predefined periods. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics. Experimental results are demonstrated by electrical simulations of an ALU circuit design.

Localization of Bugs in Processor Designs Using zamiaCAD Framework

This paper proposes an approach to automatic localization of design errors (bugs) in processor designs based on combining statistical analysis of dynamically covered VHDL code items and static slicing. The approach considers coverage of different VHDL code items including statements, branches and conditions during processor simulation which together contribute to accurate localization of bugs. The accuracy of analysis is further improved by applying a static slicing based filter calculated by means of reference graph generation using a through-signal-assignment search from the semantically resolved elaborated models of processor designs. The localization approach has been integrated to highly scalable zamiaCAD RTL design framework. The efficiency of the proposed approach is demonstrated by applying it to debugging of an industrial processor ROBSY designed for FPGA-based test systems. The experimental results evaluate the approach for a set of real documented bug cases and the original functional test.

Improved fault emulation for synchronous sequential circuits

Current paper presents new alternatives for accelerating the task of fault simulation for sequential circuits by hardware emulation on FPGA. Fault simulation is an important subtask in test pattern generation and it is frequently used throughout the test generation process. The problems associated to fault emulation for sequential circuits are explained and alternative implementations are discussed. An environment for hardware emulation of fault simulation is presented. It incorporates hardware support for fault dropping. The proposed approach allows simulation speed-up of 40 to 500 times as compared to the state-of-the-art in fault simulation. Average speedup provided by the method is 250 that is about an order of magnitude higher than previously cited in the literature. Based on the experiments, we can conclude that it is beneficial to use emulation when large numbers of test vectors is required.

Rejuvenation of NBTI-Impacted Processors Using Evolutionary Generation of Assembler Programs

The time-dependent variation caused by Negative Bias Temperature Instability (NBTI) is agreed to be one of the main reliability concerns in integrated circuits implemented with current nanotechnology nodes. NBTI increases the threshold voltage of pMOS transistors: hence, it slows down signal propagation along logic paths between flip-flops. It may cause intermittent faults and, ultimately, permanent functional failures in processor circuits. In this paper, we study an NBTI mitigation approach in processor designs by rejuvenation of pMOS transistors along NBTI-critical paths. The method incorporates hierarchical fast, yet accurate modelling of NBTI-induced delays at transistor, gate and path levels for generation of rejuvenation Assembler programs using an Evolutionary Algorithm. These programs are applied further as an execution overhead to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay in processors. The experimental results demonstrate efficiency of evolutionary generation and significant reduction of NBTI-induced delays by the rejuvenation stimuli with an execution overhead of 0.1% or less. The proposed approach aims at extending the reliable lifetime of nanoelectronic processors.

Diagnostic Test Generation for Statistical Bug Localization Using Evolutionary Computation

Verification is increasingly becoming a bottleneck in the process of designing electronic circuits. While there exists several verification tools that assist in detecting occurrences of design errors, or bugs, there is a lack of solutions for accurately pin-pointing the root causes of these errors. Statistical bug localization has proven to be an approach that scales up to large designs and is widely utilized both in debugging hardware and software. However, the accuracy of localization is highly dependent on the quality of the stimuli. In this paper we formulate diagnostic test set generation as a task for an evolutionary algorithm, and propose dedicated fitness functions that closely correlate with the bug localization capabilities. We perform experiments on the register-transfer level design of the Plasma microprocessor coupling an evolutionary test-pattern generator and a simulator for fitness evaluation. As a result, the diagnostic resolution of the tests is significantly improved.

Automated Design Error Localization in RTL Designs

This paper considers the case where a design described in a Hardware Description Language (HDL) has been identified as erroneous during functional verification and, thus, design error localization is required. However, due to the enormous complexity of modern Register-Transfer Level (RTL) designs, several bugs may escape verification and are consequently handled by post-silicon validation.

Assessment of diagnostic test for automated bug localization

Statistical simulation based design error debug approaches strongly rely on quality of the diagnostic test. At the same time there exists no dedicated technique to perform its quality assessment and engineers are forced to rely on subjective figures such as verification test quality metrics or just the size of the diagnostic test. This paper has proposed two new approaches for assessing diagnostic capability of diagnostic tests for automated bug localization. The first approach relies on probabilistic simulation of diagnostic experiments. The second assessment method is based on calculating Hamming distances of the individual sub-tests in the diagnostic test set. The methods are computationally cheap and they provide for a measure of confidence in the localization results and allow estimating impact of the diagnostic test enhancement. The approach is implemented as a part of an open-source hardware design and debugging framework zamiaCAD. Experimental results with an industrial processor design and a set of documented bugs demonstrate feasibility and effectiveness of the proposed approach.

PSL assertion checkers synthesis with ASM based HLS tool ABELITE

This paper presents a new approach for synthesizing hardware checkers from temporal assertions described in Property Specification Language (PSL). The approach utilizes Algorithmic State Machines (ASMs) based High Level Synthesis (HLS) tool ABELITE. It targets creation of functionally and temporally correct checkers that provide comprehensive assertion checking debug information during emulation. The paper contributions include a new methodology for PSL assertions translation to ASM representations and a new approach for the HLS tool ABELITE application for correct by construction assertion generation. Experimental results demonstrate feasibility and effectiveness of the proposed approach.