Vanessa Vargas

Evaluating SEU fault-injection on parallel applications implemented on multicore processors

The widespread use of multicore processors in computing systems and the imperative necessity of exploiting massive parallelism to improve performance and dependability, make mandatory to evaluate the impact of SEUs on parallel applications running on multicore processors. This paper presents a method and preliminary results of SEU fault-injection campaigns performed on parallel applications implemented on a quad-core processor. Two representative benchmarks applications were considered for the analysis.

Radiation Experiments on a 28 nm Single-Chip Many-Core Processor and SEU Error-Rate Prediction

This work evaluates the SEE static and dynamic sensitivity of a single-chip many-core processor having implemented 16 compute clusters, each one with 16 processing cores. The SEU error-rate of an application implemented in the device is predicted by combining experimental results with those issued from fault injection campaigns applying the CEU (Code Emulating Upsets) approach. In addition, a comparison of the dynamic tests when processing-cores cache memories are enabled and disabled is presented. The experiments were validated through radiation ground testing performed with 14 MeV neutrons on the MPPA-256 many-core processor manufactured in TSMC CMOS 28HP technology. An analysis of the erroneous results in processor GPRs was carried-out in order to explain their possible causes.

Single Events in a COTS Soft-Error Free SRAM at Low Bias Voltage Induced by 15-MeV Neutrons

This paper presents an experimental study of the sensitivity to 15-MeV neutrons of Advanced Low Power SRAMs (A-LPSRAM) at low bias voltage little above the threshold value that allows the retention of data. This family of memories is characterized by a 3D structure to minimize the area penalty and to cope with latchups, as well as by the presence of integrated capacitors to hinder the occurrence of single event upsets. In low voltage static tests, classical single event upsets were a minor source of errors, but other unexpected phenomena such as clusters of bitflips and hard errors turned out to be the origin of hundreds of bitflips. Besides, errors were not observed in dynamic tests at nominal voltage. This behavior is clearly different than that of standard bulk CMOS SRAMs, where thousands of errors have been reported.

Evaluating the SEE Sensitivity of a 45 nm SOI Multi-Core Processor Due to 14 MeV Neutrons

The aim of this work is to evaluate the SEE sensitivity of a multi-core processor having implemented ECC and parity in their cache memories. Two different application scenarios are studied. The first one configures the multi-core in Asymmetric Multi-Processing mode running a memory-bound application, whereas the second one uses the Symmetric Multi-Processing mode running a CPU-bound application. The experiments were validated through radiation ground testing performed with 14 MeV neutrons on the Freescale P2041 multi-core manufactured in 45 nm SOI technology. A deep analysis of the observed errors in cache memories was carried-out in order to reveal vulnerabilities in the cache protection mechanisms. Critical zones like tag addresses were affected during the experiments. In addition, the results show that the sensitivity strongly depends on the application and the multi-processing mode used.

Preliminary results of SEU fault-injection on multicore processors in AMP mode

The current technological challenge for computing systems is to use multicore processors in order to ensure reliability, improve performance, and reduce power consumption. This paper presents a method and preliminary results of SEU fault-injection campaigns performed on multicore systems in asymmetric multi-processing mode. The target used for this purpose was a Quad-core processor. This work aims at validating the efficiency of TMR fault-tolerance method and to show the weakest variables of a given application running over multicore systems.

Neutron-Induced Single Events in a COTS Soft-Error Free SRAM at Low Bias Voltage

This paper presents an experimental study of the sensitivity to 15-MeV neutrons at low bias voltage of advanced low-power SRAMs by Renesas Electronics. The most interesting results are the occurrence of clusters of bitflips, hard errors only visible at low voltage, appearing along with single event upsets. The physical mechanisms are briefly discussed.

Assessing the Static and Dynamic Sensitivity of a Commercial Off-the-Shelf Multicore Processor for Noncritical Avionic Applications

The present work assesses the radiation sensitivity of an affordable and performant COTS multicore processor for noncritical avionic applications. The target device is the Epiphany E16G301 multicore manufactured in 65 nm CMOS which integrates 16 processor cores. This device was selected due to its high performance, low power consumption, and affordability, allowing general public accessing to parallel computing. Additionally, the E16G301 is the coprocessor for parallel processing of the Parallella platform, which was considered by NASA researchers for onboard health management of the DragonEye UAS. The evaluation of the device is done using quantitative theory by means of radiation experiments with 14 MeV neutrons to emulate the effects of high-energy neutrons present at avionic altitudes. Static and dynamic cross sections are obtained to evaluate the intrinsic sensitivity of the device as well as its dynamic response. Results show that the failure rate of the E16G301 running a matrix multiplication as application reaches level D of the DO-178B/C guideline, being the device well suited for minor failure conditions of avionic applications.

Sensitivity to Neutron Radiation of a 45 nm SOI Multi-Core Processor

The purpose of this paper is to evaluate the SEU sensitivity of a multi-core SoC working in two different multiprocessing modes. Radiation ground tests were performed with 14 MeV neutrons in GENEPI2 facility. The case study was a 45nm SOI multi-core processor having implemented error correcting code (ECC) and parity in their cache memories.