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Dive into the research topics where Sheila Chopin is active.

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Featured researches published by Sheila Chopin.


IEEE Transactions on Electronics Packaging Manufacturing | 2006

A Statistical Study of Sn Whisker Population and Growth During Elevated Temperature and Humidity Tests

Peng Su; Jim Howell; Sheila Chopin

Storage tests at elevated temperature and humidity conditions have been widely adopted as one of the major acceleration tests for Sn whisker growth. However, the driving force associated and the nucleation and growth process of whiskers are yet to be fully understood. In this paper, Sn whisker growth on Cu leadframe material at two different test conditions is compared. Both loose and board-mounted components were used. At each read point, the length and location of every whisker observed was recorded. Statistical characteristics and growth rate of the whisker population will be presented for each of the tests conditions. On loose components, corrosion of the Sn finish was observed near the tip and the dam bar cut area of the leads with backscatter scanning electron microscopy (SEM) and optical microscopy. The entire population of whiskers was located in these corroded areas, and there were zero whiskers located in the noncorroded areas on the same leads. On board-mounted components, the corrosion level of the Sn finish, as well as the whisker population and length was greatly reduced compared to those on the loose components. These results suggest that the corrosion of Sn finish in high-temperature and high-humidity conditions is the major driving force for whisker growth. The cause for the difference between the loose and board-mounted components is also analyzed


IEEE Transactions on Electronics Packaging Manufacturing | 2006

Microstructure-Based Stress Modeling of Tin Whisker Growth

Jie-Hua Zhao; Peng Su; Min Ding; Sheila Chopin; Paul S. Ho

A 3D finite element method (FEM) model considering the elasticity anisotropy, thermal expansion anisotropy and plasticity of /spl beta/-Sn is established. The Voronoi diagrams are used to generate the geometric patterns of grains of the Sn coating on Cu leadframes. The crystal orientations are assigned to the Sn grains in the model using the X-ray diffraction (XRD) measurement data of the samples. The model is applied to the Sn-plated package leads under thermal cycling tests. The strain energy density (SED) is calculated for each grain. It is observed that the samples with higher calculated SED are more likely to have longer Sn whiskers and higher whisker density. The FEM model, combined with the XRD measuring of the Sn finish, can be used as an effective indicator of the Sn whisker propensity. This may expedite the qualification process significantly.


electronic components and technology conference | 2005

Effects of reflow on the microstructure and whisker growth propensity of Sn finish

Peng Su; Min Ding; Sheila Chopin

The initiative of removing Pb from materials sets within the microelectronics industry has created many challenges for research and development. One of the issues is to replace the Pb-containing finish with a Pb-free finish for leaded packages. Pure Sn and alloys with high Sn content have been the leading choices for many manufacturers. These finishes, however, have the tendency to spontaneously grow whiskers on the surface, which is considered by some to be a potential reliability concern as the whiskers can continuously grow and may cause shorting between leads. In this study, leaded components with as-plated Sn finish and reflowed Sn finish are subjected to several Sn whisker acceleration tests including air-to-air thermal cycling and temperature/humidity storage. The results indicate that the whisker growth propensity on the two different finishes is rather different. Microstructure analysis of the Sn finish is also performed with scanning electron microscopy (SEM), X-ray diffraction (XRD), and electron backscatter diffraction (EBSD). Significant microstructure differences are observed between the as-plated and the reflowed Sn finish including grain size, grain orientation, and intermetallic compound (IMC) thickness. As Sn whisker growth is mostly a stress related phenomenon, these findings of microstructure change are used to interpret the process of stress buildup and relief in both as-plated and reflowed Sn. Additionally, at room temperature Sn has a very anisotropic lattice (body centered tetragonal) and this property contributes greatly to the stress concentration in the Sn finish. The implication of this property on Sn whisker growth is also discussed.


electronic components and technology conference | 2005

Effects of trim and form on the microstructure and whisker growth propensity of Sn finish

Min Ding; Peng Su; Sheila Chopin

A microstructure study was performed on electroplated Sn finish on leadframes both before and after the forming process. Two types of plastic quad flat pack (QFP) packages of different dimensions were used. On the leadframes prior to the forming process, the Sn plating had a very uniform grain size. After the trim/form process, however, the grain size was considerably larger at the deformed areas on the leads, while the non-deformed areas maintained their grain size. This difference is believed to be caused by the recrystallization and growth of the deformed Sn plating. The same post-forming packages were also subject to two types of accelerated whisker growth tests. After the tests both the density and maximum length of whiskers in the deformed areas on the leads are reduced compared to the non-deformed areas. Considering the theory that Sn whisker growth is driven by the compressive stress buildup in the finish, these results are explained by the facts that grain recrystallization and growth relieves the pre-existing stress in the finish and reduces the triple points and grain boundaries in the plating. Based on these findings, it is concluded that Sn finishes with larger grain sizes would have less whisker growth. Dimension of the leads on packages may also affect the overall whisker growth propensity due to the difference in the size of deformation zones.


international electronics manufacturing technology symposium | 2007

Pb-free BGA Solder Joint Reliability Improvement with Sn3.5Ag Solder Alloy on Ni/Au Finish

Eu Poh Leng; Min Ding; Wayne Lindsay; Sheila Chopin; Ibrahim Ahmad; Azman Jalar

In this work, Sn3.5Ag solder alloy was being studied for the purpose of Pb-free solder joint reliability improvement over conventional Sn3.8AgO.7Cu solder balls on Ball Grid Array (BGA) packages with Ni/Au pad finishing. The study was carried out in different levels. At individual solder joint level, Sn3.5Ag showed no intermetallic brittle failure in cold ball pull test even up to 6times multiple reflow and 168 hrs high temperature storage for TBGA & TePBGA, and 504 hrs high temperature storage for PBGA Spanish Oak. In contrast, 70-100% of the failure mode of SAC387 was brittle failure. At package level, Sn3.5Ag survived 8~10x more drop cycles than SAC387 in tray drop and packing drop tests. These results indicate that the mechanical strength of Sn3.5Ag on Ni/Au pad is considerably stronger than that of SAC387. The difference in mechanical strength between the two alloys was correlated to their microstructures. At the same time, board level solder joint reliability tests such as thermal cycling and mechanical bend test were carried out. Sn3.5Ag showed better or similar performance as SAC387.


electronic components and technology conference | 2007

A Comparative Study of Sn3.5Ag and Sn3.8Ag0.7Cu for BGA Spheres on Ni/Au Finish

Poh-Leng Eu; Huey-Jiun Hoh; J. Rayos; Peng Su; W. Lindsay; Sheila Chopin; I. Ahmad

A comparative study was conducted with Sn3.5%Ag and Sn3.8%Ag0.7%Cu solder balls on ball grid array (BGA) packages with Ni/Au pad finishing. The study was carried out in different levels. At individual solder joint level, Sn3.5Ag showed no intermetallic brittle failure in cold ball pull test under any stress condition. In contrast, 70-100% of the failure mode of SAC387 was brittle failure. At package level, Sn3.5Ag survived 8~10x more drop cycles than SAC387 in tray drop and packing drop tests. These results indicate that the mechanical strength of Sn3.5Ag on Ni/Au pad is considerably stronger than that of SAC387. The difference in mechanical strength between the two alloys was correlated to their microstructures. At the same time, board level solder joint reliability tests such as thermal cycling and mechanical bend test were carried out. Sn3.5Ag showed similar performance as SAC387. The reason for the similarity was also explained by examining the microstructure change that occurred during board mounting process.


electronics packaging technology conference | 2013

Challenges and resolutions of Pd-Cu wire bond biased HAST failures from additive particle in the green mold compound

Serene Teh Seoh Hian; Sheila Chopin; S. S. Skh Ali

In recent years there were numerous reported failures of Cu wire packages after moisture related reliability stress such as biased HAST (highly accelerated stress test) due to corrosion of copper-aluminum intermetallics by trace amounts of chlorine in mold compound. As such mold compound selection and certification are of critical importance to ensure good reliability of packages with copper (Cu) wire. In this paper, we report continuity opens after 192 hours of biased HAST at 130C/85% RH on two devices (Y and P) using existing production green mold compounds. The failure was due to a large additive particle adhering to the Palladium-Copper (Pd-Cu) ball bond. Modifications were made in mold compound raw material milling or crushing process to ensure a more homogenous blend of particles to eliminate the occurrence of such large additive particles in the mold compound. Despite this, large additive particle are still found occasionally as the raw material supplier could not effectively control the maximum size of the particles. Further improvements were then made by using a super homogenizer milling process on blended compound ingredients and a fine sieve to sieve out the large particles from the formulation. This approach was found to work exceptionally well with excellent moldability, reliability and delamination performance. In conclusion, optimum compound formulation and compound fabricating processes are essential factors to ensure reliable performance of Pd-Cu devices in Low Quad Flat Packages (LQFP).


international conference on electronic packaging technology | 2010

Failure observations and mechanical modeling

Yuan Yuan; Min Ding; Sheila Chopin

Mechanical simulation and modeling play increasingly important roles in semiconductor industry. It provides guidelines on material selection, package geometry configuration, and package platform selection. It also provides insights and predictions on package reliability and failure mechanisms. Many mechanical models on reliability and failure issues aim directly at observed failures, such as solder cracks or die cracks. Simulations based on straightforward observations from failures are often correct, but not always. For example, failure analysis (FA) photos are usually taken at room temperature showing a static failure moment. This may not provide true “failure mode” at the failure temperature, and may miss the dynamic motion of the procedure. Therefore, the observed failures need to be carefully analyzed to discover the true failure mode and failure mechanism. These analyses may lead to different failure mechanism and result in simulations of different focus for improvements. This paper provides a few examples on semiconductor package failures and the analysis processes: how the FA photos lead to the discovery of the true failure mechanisms and how FEM simulation helped solving these issues.


Archive | 2004

Solderable metal finish for integrated circuit package leads and method for forming

Peng Su; Sheila Chopin; Nhat D. Vo


Archive | 2003

Warpage control of array packaging

Yuan Yuan; Sheila Chopin

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Min Ding

Freescale Semiconductor

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Peng Su

Freescale Semiconductor

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Yuan Yuan

Freescale Semiconductor

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Jie-Hua Zhao

Freescale Semiconductor

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Nhat D. Vo

Freescale Semiconductor

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Paul S. Ho

University of Texas at Austin

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