Venkat R. Kolagunta

A novel biasing technique for addressable parametric arrays

Addressable arrays that use switches to isolate the devices being tested are limited in size and utility by the parasitic leakage caused by those switches. A new biasing technique that reduces the leakage of these switches has been studied to address this problem. Simulations performed in a 90 nm low-power technology predicted almost a two-decade drop in parasitic leakage of the array. Experimental data confirmed this improvement. 1 times 32 and 4 times 32 arrays using this biasing technique were used to investigate probe pad effects, device variability and geometry dependence.

Multi-Layer Model for Stressor Film Deposition

Multi-layer simulation is proposed for accurate modeling of stressor film deposition. Multi-layer simulation subdivides a single deposition into a series of deposition and relaxation steps to emulate mechanical quasi-equilibrium during the physical deposition process. Only the multi-layer model is able to simultaneously match the experimental data on drive current vs. etch-stop layer stress, poly pitch, source/drain recess, and spacer stress

Modeling and Simulation of Poly-Space Effects in Uniaxially-Strained Etch Stop Layer Stressors

We develop, for the first time, a compact and scalable model to account for the poly-space effects (PSEs) in uniaxially-strained etch stop layer (ESL) stressors. The model is based on 2-dimensional (2D) finite element (FEM) stress simulations and 4-point bending characterization of silicon, and agrees well with measured data. The impact of PSEs on circuit performance is also discussed.

A Novel Biasing Technique for Addressable Parametric Arrays

Addressable arrays that use switches to isolate the devices being tested are limited in size and utility by the parasitic leakage caused by those switches. A new biasing technique that removes the drain-source bias from these switches has been studied to address this problem. Simulations performed in a 90 nm low-power technology predicted more than a two-decade drop in parasitic leakage of the array. Experiment data performed on a 90 nm technology confirmed this improvement.

Optimization of Dual-ESL Stressor Geometry Effects for High Performance 65nm SOI Transistors

We report on the optimized transverse and lateral boundaries of dual etch stop layer (dESL) stressors in both PMOS and NMOS achieved in 65nm SOI transistors. We demonstrate that this gives an additional ~20% performance gain in ring oscillators. The optimization takes into account the 1-D and 2-D geometry effects, including poly-pitch, and is in good agreement with stress simulations

High Performance NMOS Transistors for 45nm SOI Technologies

We demonstrate NMOS performance enhancements of up to ~18% for applications in a 45 nm SOI technology. The performance boost was achieved using high tensile-stressed UV film in conjunction with stress memorization techniques (SMT). For the first time we demonstrate that using a UV-cured tensile film allows a 6% performance boost on the SOI NMOS, achieving a drive current of ~1170 muA/mum (1250, non-self-heated) at Ioff = 100 nA/mum, Vdd = 1 V.

High performance, highly reliable FD/SOI I/O MOSFETs in contemporary high-performance PD/SOI CMOS

Integration of fully-depleted SOI (FD/SOI) MOSFETs for high performance 3.3 V/2.5 V I/O applications in contemporary high-performance partially-depleted SOI (PD/SOI) CMOS is reported for the first time. The FD/SOI MOSFETs feature dual etch-stop layer (dESL) stressor, optimized (minority) carrier lifetime killing implant in source/drain extension, and optimized in-situ steam generated (ISSG) gate oxidation process.

Performance Enhancement via Laser Anneal-Based RS/D Reduction in PD/SOICMOS

Extrinsic source/drain series resistance (RSD/) becomes a limiting factor as performance boosters, such as strain-Si and metal-gate/high-k gate stack that enhance the intrinsic MOSFET, are vigorously pursued and implemented in nanoscale CMOS (Ghani, et al., 2003). Non-melt laser spike anneal (LSA) (Feng et al., 2004) has been suggested (Shima, et al., 2004), (Fung et al., 2004) as a means to reduce RSD/. In this paper, we present, for the first time, application of LSA to 35nm gate length, high-performance PD/SOI CMOS with dual etch stop layer (dESL) stressors and NiSi (Grudowski et al., 2006), showing 10% (4%) nFET (pFET) on-state current (Ion) enhancement and non-self-heated Ion=1520/1160muA/mum (880/630muA/mum) at VDD=1.2V/1.0V

Characteristic Study of SOI eSiGe Techonology

This paper presents a detailed study of SOI source/drain embedded SiGe (eSiGe) technology with a focus on parasitic characteristics. It shows that eSiGe can appreciably suppress on-state floating body effect and improve device exterior resistance. Although eSiGe only physically addresses P-FET, junction capacitances of both P- and N-FETs can be impacted.