Vance H. Adams

Opposing dependence of the electron and hole gate currents in SOI MOSFETs under uniaxial strain

The influence of tensile mechanical stress on ultrathin oxide gate currents in advanced partially depleted silicon-on-insulator MOSFETs is reported. Strain is applied uniaxially, perpendicular to the direction of current flow by bending of thinned, fully processed wafers with a gate oxide thickness of less than 1.5 nm. The gate currents of the n-channel and p-channel MOSFETS are found to change linearly and in opposite (opposing) directions as a function of uniaxial strain. The nMOS transistors generally exhibit a decrease with applied tensile strain, while the nMOS transistors show increasing gate current with strain. The observed dependences are consistent with a gate current controlled by direct tunneling and perturbed by stress-induced changes in the energy band structure.

1-D and 2-D Geometry Effects in Uniaxially-Strained Dual Etch Stop Layer Stressor Integrations

We report, for the first time, on the 2D boundary effects in a high performance 65nm SOI technology with dual etch stop layer (dESL) stressors. 1D geometry effects, such as poly pitch dependence, and the implications on SPICE models and circuit design are also discussed. It will be shown that PMOS and ring oscillator performance can be significantly enhanced by optimizing the transverse and lateral placement of the dESL boundary

Embedded SiGe S/D PMOS on thin body SOI substrate with drive current enhancement

We report for the first time PMOS drive current enhancement with in-situ boron doped SiGe incorporation in recessed S/D regions for devices built on thin body SOI substrate. For P-channel PD-SOI devices with 450 A silicon on insulator and 38nm gate length, 35% linear drain current enhancement and 20% saturation drain current improvement have been achieved with this approach. Device integration and performance improvement are discussed below.

Micro-scale measurement and modeling of stress in silicon surrounding a tungsten-filled through-silicon via

The stress in silicon surrounding a tungsten-filled through-silicon via (TSV) is measured using confocal Raman microscopy line scans across the TSV both before and after etch removal of an oxide stack used as a mask to define the TSV during fabrication. Stress in the silicon arose in response to both athermal deposition and thermal expansion mismatch effects. The complex three-dimensional stress and strain field in silicon surrounding the TSV is modeled using finite element analysis, taking into account both athermal and thermal effects and the elastic anisotropy of silicon. Comparison of the measurements and model results shows that no one component of the stress tensor correlates with the Raman peak shift generated by the deformed silicon. An analysis is developed to predict the Raman shift in deformed silicon that takes into account all the components of the stress or strain tensor; the results of the model are then used as inputs to the analysis for direct comparison with measured peak shifts as a fun...

Strain-Enhanced CMOS Through Novel Process-Substrate Stress Hybridization of Super-Critically Thick Strained Silicon Directly on Insulator (SC-SSOI)

This paper describes a biaxial-uniaxial hybridized strained CMOS technology achieved through selective uniaxial relaxation of thick SSOI, dual-stress nitride capping layer, and embedded SiGe source/drain. Through novel strain engineering, nFET/pFET Idsat enhancements as high as 27%/36% have been achieved for sub-40nm devices at 1V with 30% reduction in gate leakage current, while introducing minimum process complexity. This work demonstrates the scalability of SC-SSOI and its advantages over pure biaxial and single uniaxial strained Si technologies

Multi-Layer Model for Stressor Film Deposition

Multi-layer simulation is proposed for accurate modeling of stressor film deposition. Multi-layer simulation subdivides a single deposition into a series of deposition and relaxation steps to emulate mechanical quasi-equilibrium during the physical deposition process. Only the multi-layer model is able to simultaneously match the experimental data on drive current vs. etch-stop layer stress, poly pitch, source/drain recess, and spacer stress

Modeling and Simulation of Poly-Space Effects in Uniaxially-Strained Etch Stop Layer Stressors

We develop, for the first time, a compact and scalable model to account for the poly-space effects (PSEs) in uniaxially-strained etch stop layer (ESL) stressors. The model is based on 2-dimensional (2D) finite element (FEM) stress simulations and 4-point bending characterization of silicon, and agrees well with measured data. The impact of PSEs on circuit performance is also discussed.

Thermo-mechanical stress characterization of tungsten-fill through-silicon-via

Thermo-mechanical stress of tungsten-filled (W-fill) through-silicon-via (TSV) is strongly depending on via shape, size and inter-via spacing, which places constraints on TSV design, including 2-D integrated circuit layout and 3-D structure profile. This paper summarizes these constraints and co-relations among thick (up to 1.2µm) tungsten (W) film, W-fill TSV, and surrounding silicon structures, using Flexus bowing measurement, Wright etch method, and also 3-D TSV stress simulations. In this study, the stress was found to be primarily tensile, and tended to be much higher along the longitudinal ends of the TSV compared to the longitudinal side wall. For an isolated TSV of given width and depth: with 30µm length the stress is 45% greater compared to the case of 7µm length. For an array of TSV with given length, width, and depth: larger spacing along the longitudinal axis (length directions) resulted in 35% lower stress at the longitudinal ends of the TSV, while smaller spacing along the transverse axis (width directions) of the TSV resulted in a 46% lower tensile stress. However, along the longitudinal side walls, the tensile stress increases by 200 MPa as the spacing along the transverse axis decreases between neighboring TSV.

Through-Silicon-Via stress 3D modeling and design

Through-Silicon-Via (TSV) processing is critical to 3D chip stacked integrated circuit (IC) technology. The understanding and management of the induced stresses in silicon due to coefficient of thermal expansion (CTE) mismatch is critical for the successful implementation of this process in circuit design and production. Most TSVs in these applications are copper (Cu) filled. Analysis of Cu-filled TSV induced stress has been reported by Okoro et. al [1], and the proposed stress measurement and model has been reported by Chidambaram et. al. [2].

An Embedded Silicon-Carbon S/D Stressor CMOS Integration on SOI with Enhanced Carbon Incorporation by Laser Spike Annealing

We report a CMOS-compatible embedded silicon-carbon (eSiC) source/drain stressor technology with NMOS performance enhancement. The integration includes up to 2.6% substitutional carbon (Csub) epitaxial Si:C and laser spike annealing (LSA) for increased Csub incorporation. 26% channel resistance (Rch) reduction and 11% Idlin-Ioff enhancement for 0.5% Csub and 60% Rch reduction for 2.2% Csub are demonstrated.