Mariam G. Sadaka

Metrology Challenges for 45 nm Strained‐Si Devices

The semiconductor industry has sustained its historical exponential performance gains by aggressively scaling transistor dimensions. However, as devices approach sub‐100 nm dimensions, scaling becomes more challenging and new materials are required to overcome the fundamental physical limits imposed by existing materials. For example, as power supply voltages continue to decrease with successive scaling, enhanced carrier mobility using biaxially tensile‐strained‐Si on SOI or on bulk substrates have become viable options to sustain continual drive current increases without traditional scaling. Although the addition of strained‐Si to conventional MOSFET devices is compatible with existing mainstream CMOS process technology, there are new device and process integration challenges, wafer quality monitoring demands, and stringent requirements for film morphology and strain uniformity, imposing new demands on material characterization. Material requirements for strained‐Si CMOS devices include homogeneous Si or...

Integration challenges of new materials and device architectures for IC applications

In this paper, we will detail the issues with new materials being introduced into CMOS devices and present some potential solutions to enable high performance and low power CMOS for the 65nm node and beyond.

Transmission Electron Microscopy Studies of Strained Si CMOS

In this paper, various types of defects (both threading dislocation and misfit dislocations) in strained Si (sSi) have been analyzed by transmission electron microscopy (TEM). Germanium upper-diffusion has been studied by scanning transmission electron microscopy (STEM) for strained Si on SiGe/SOI. SGOI-devices processed using an optimized thermal budget show minimal Ge diffusion and minimal process related defects. Correlation between the device performance (such as leakage current and reliability) and structural information found in TEM has been established.

Fabrication and operation of sub-50 nm strained-Si on Si/sub 1-x/Ge/sub x/ Insulator (SGOI) CMOSFETs

First functional 45 nm SGOI CMOS devices on bonded SGOI substrates with T/sub SOI/<45 nm exhibited superior short-channel control and comparable reliability to SOI devices. A 67% Gm enhancement was observed in long-channel nMOS SGOI devices, 18% drive current increase for short-channel SGOI devices, and 12% faster ring-oscillators were exhibited with respect to control SOI devices. Functional SRAM bit cells down to V/sub dd/=0.9 V were also demonstrated.