Venkata P. Yanambaka

Reconfigurable Robust Hybrid Oscillator Arbiter PUF for IoT Security Based on DL-FET

The Internet of Things (IoT) is currently a main focus of research across disciplines. In a household IoT environment, almost all devices are connected to the internet. In the case of a smart city, most of the city homes and departments are managed through the network. One small security vulnerability is enough to take down an entire city or parts of it. Hence communications should be encrypted. Physical Unclonable Functions are commonly used for this purpose. A PUF key is not stored anywhere thus providing the advantage of secrecy. In the current paper, two designs of a reconfigurable PUF are proposed, a speed optimized reconfigurable hybrid oscillator arbiter PUF and its power optimized counterpart. Both designs can be introduced into two different categories of IoT devices, one where high performance is needed and one with low power consumption. The Hamming distance of the speed optimized and power optimized designs is 47 % and 48 % with power consumption of 167.5 µW and 143.3 µW, respectively.

Ultra-fast variability-aware optimization of mixed-signal designs using bootstrapped kriging

Analog/Mixed-Signal (AMS) circuits present significant challenges to designers with the increase of design complexity and aggressive technology scaling. Design optimization techniques that account for process variation while presenting an accurate and fast design flow which can perform design optimization in reasonable time are still lacking. As a trade-off of the accuracy and speed, this paper presents a process-variation aware design flow for ultra-fast variability-aware optimization of nano-CMOS based physical design of analog circuits. It combines Kriging bootstrapped Neural Network (KBNN) metamodels with a Particle Swarm Optimization (PSO) algorithm in the design optimization flow. The KBNN provides a trade-off between analog-quality accuracy and scalability and can be effectively used for large and complex AMS circuits while capturing correlations in process variations. The effectiveness of the design flow is demonstrated using a 180nm CMOS based PLL as a case study with 21 design parameters. The KBNN metamodel is 24× faster than NN metamodeling.