Dhruva Ghai

Comparative analysis of double gate FinFET configurations for analog circuit design

FinFETs are being adopted as an alternative to nanoscale classical MOSFET for digital circuits. The double-gate (DG) FinFET gives rise to a rich design space using various configurations of the gates. Existing research study the DG FinFET for digital design. However, the effectiveness of the various DG FinFET configurations for the analog design has not received much attention. In this paper, we compare the DG FinFET parameters including transconductance (gm), output resistance (r0), open-circuit gain (gm × r0), transition frequency (fT) including the most important issue, “nanoscale variability”, which are important for analog design. The following three configurations for a fully depleted SOI DG FinFET are analyzed: shorted-gate, independent-gate, and low-power, for both strong inversion and subthreshold operations. Using the results obtained, we present guidelines for DG FinFET based analog design.

Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments

We propose a novel design f ow for mismatch and processvariation aware optimization of nanoscale CMOS Active Pixel Sensor (APS) arrays. As a case study, an 8 × 8 APS array is designed using the proposed methodology for 32nm CMOS technology. Performance metrics such as power, output voltage swing, dynamic range (DR) and capture time (delay) have been measured. The baseline results show a power consumption of 16.32µW, output voltage swing of 428mV, dynamic range (DR) of 59.47dB and a capture time of 5.65µs. The baseline APS array is subjected to 5% ¿intra-pixel¿ mismatch and 10% ¿inter-pixel¿ process variation and the effect on power and output voltage swing has been observed. The APS array is subjected to a design and analysis of Monte Carlo experiments based optimization. Using this approach, we have been able to achieve 21% reduction in power (including leakage). To the best of our knowledge, this is the f rst ever nano-CMOS implementation of an APS array optimized to be mismatch and process variation tolerant.

Fast optimization of nano-CMOS voltage-controlled oscillator using polynomial regression and genetic algorithm

Fast optimization of CMOS circuits is needed to reduce design cycle time and chip cost and to enhance yield. Mature electronic design automation (EDA) tools and well-defined abstraction-levels for digital circuits have largely automated the digital design process. However, analog circuit design and optimization is still not automated. Custom design of analog circuits and slow analog in SPICE has always needed maximum efforts, skills and design cycle time. In this paper, two novel design flows are presented for fast multiobjective optimization of nano-CMOS circuits: actual-value optimization and normalized-value optimization. The design flows consider two characteristics for optimization i.e. power and frequency in a current-starved 50nm voltage-controlled oscillator (VCO). Accurate polynomial-regression based models have been developed for power (including leakage) and frequency of the VCO to speedup the design optimization. In the actual-value optimization flow, the power model is minimized using genetic algorithm, while treating frequency >=100MHz as a constraint. The actual-value optimization flow achieved 21.67% power savings, while maintaining a frequency >=100MHz. In the normalized-value optimization flow, the normalized form of these models are subjected to a weighted optimization using genetic algorithm. The normalized-value optimization flow achieved 16.67% power savings, with frequency >=100MHz. It is observed that while the actual-value optimization approach provides a better exploration of the design space, the normalized-value optimization approach provides a ~5x speedup in the computation time.

A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM

A novel design approach for simultaneous power and stability (static noise margin, SNM) optimization of nano-CMOS static random access memory (SRAM) is presented. A 45nm single-ended seven transistor SRAM is used as a case study. The SRAM is subjected to a dual-VTh assignment using a novel combined Design of Experiments and Integer Linear Programming (DOE-ILP) algorithm, resulting in 50.6% power reduction (including leakage) and 43.9% increase in the read SNM. The process variation analysis of the optimal SRAM carried out considering twelve device parameters shows the robustness of the design.

A universal level converter towards the realization of energy efficient implantable drug delivery Nano-Electro-Mechanical-Systems

Nano-Electro-Mechanical-Systems (NEMS) are a technological solution for building miniature systems which can be beneficial in terms of safety, efficacy, or convenience. Thus investigation is necessary for their usefulness in drug delivery. In order to be an effective and reliable implantable system the DDNEMS (Drug Delivery Nano-Electro-Mechanical-System) should have low power dissipation, fault tolerance, and reconfigurability capabilities. In this paper we introduce a DDNEMS architecture, identify its major components, and propose the design of the crucial component universal (voltage) level converter (ULC). The ULC is a unique component that will reduce dynamic power and leakage of DDNEMS while facilitating its reconfigurability. The ULC is capable of performing level-up and level-down conversions and can block an input signal. We have prototyped a ULC using 32nm high-k/metal-gate nano-CMOS technology with dual-VTh technique. The robustness of the design is tested by carrying out three types of analysis, namely: parametric, load and power. It is observed that the ULC produces a stable output for voltages as low as 0.35V and loads varying from 50fF to 120fF. The average power dissipation of the proposed level converter with a 82fF capacitive load is 5µW.

A process and supply variation tolerant nano-CMOS low voltage, high speed, a/d converter for system-on-chip

This paper presents a process variation tolerant, SoC ready, 1 GS/s, 6 bit flash analog-to-digital converter (ADC) suitable for integration into nanoscale digital CMOS technologies. The physical design is carried out with a generic 90 nm Salicide 1.2 V/2.5 V 1 Poly 9 Metal process design kit using Design for Manufacturability (DFM) methodologies. Post-layout simulation results at nominal supply and threshold voltages are presented. The parasitic-extracted physical design of the ADC has been simulated for a supply voltage variation of 10%, and threshold voltage mismatch of 5%. The results show maximum variations of 10.5% and 5.7% in the INL and DNL respectively, with nominal INL = 0.344 LSB and nominal DNL = 0.459 LSB, at a supply voltage of 1.2 V. The ADC consumes a peak power of 5.794 mW and an average power of 3.875 mW. The comparators used in the ADC have been designed using the threshold inverting technique.

A P4VT (Power Performance Process Parasitic Voltage Temperature) Aware Dual-VTh Nano-CMOS VCO

We present the design flow for a P4VT (Power-Performance-Process-Parasitic-Voltage-Temperature) aware voltage controlled oscillator (VCO). Through simulations, we have shown that parasitics, process, voltage and temperature have a drastic effect on the performance (center frequency) of the VCO. A design optimization of the VCO, along with dual-threshold power minimization has been performed in the presence of worst-case variations. The end product of the proposed methodology is a P4VT-optimal dual-threshold 90nm VCO layout. We have achieved 16.4% power (including leakage) minimization with 10% degradation in center frequency compared to the target frequency, in the presence of worst-case variations.

Variability-aware design of double gate FinFET-based current mirrors

With the technology trend moving towards smaller geometries and improved circuit performances, multigate transistors are expected to replace the traditional bulk devices. The double-gate FinFET lends itself to a rich design space using various configurations of the two gates. Accurate current mirroring is a critical analog design requirement in many applications. Current mirror is an essential component in analog design for biasing and constant current generation. This paper presents the exploration of different configurations of a double gate fully depleted SOI based FinFETs for efficient design of current mirror designs. In particular, comparison among the important Figures-of-Merit (FoMs) current mirror designs including mismatch, variability, output resistance (

A DOE-ILP assisted conjugate-gradient based power and stability optimization in High-K Nano-CMOS SRAM

r_0

A variability tolerant system-on-chip ready nano-CMOS analogue-to-digital converter

), compliance voltage (