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Dive into the research topics where Wai Lo is active.

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Featured researches published by Wai Lo.


Journal of The Electrochemical Society | 2005

Deposition and Characterization of Polycrystalline Si1 − x Ge x Films for CMOS Transistors Gate Electrode Applications

Wai Lo; Hong Lin; Wei-jen Hsia; Colin Yates; Verne Hornback; Jim Elmer; Wilbur G. Catabay; Mohammad R. Mirabedini; Venkatesh P. Gopinath; Erhong Li; David Pachura; Joyce Lin; Lesly Duong; Sharad Prasad; Masanobu Matsunaga; Toshitake Tsuda

Polycrystalline Si 1 - x Ge x (poly-SiGe) is a known gate electrode material that can mitigate poly-depletion effects, which exist in deep submicrometer complementary metal-oxide-semiconductor (CMOS) transistors, due to its lower dopant activation temperatures and smaller bandgaps. As an important step toward the manufacturing of poly-SiGe electrode-based CMOS transistors with enhanced performances, this study focuses on the deposition of poly-SiGe films with different structural features and the characterization of the physical properties of these films. The electrical performance and the reduction in poly-depletion effects of the poly-SiGe electrodes in capacitors fabricated using these films were verified using capacitance-voltage measurements.


Journal of The Electrochemical Society | 2005

Process Characterization and Control of Polycrystalline SiGe as the Gate Electrode in CMOS Fabrication

Hong Lin; Wai Lo; Shiqun Gu; Verne Hornback; Jim Elmer; Wilbur G. Catabay

Polycrystalline Si 1 - x Ge x (poly-SiGe) films have been proposed as a promising alternative to the currently employed polycrystalline silicon (poly-Si) gate electrode for complementary metal-oxide-semiconductor (CMOS) field effect transistor technology due to lower resistivity, less boron penetration, and less gate depletion than that of poly-Si gate. The use of Poly-SiGe as the gate electrode, however, has serious implications on transistor fabrication processes such as plasma dry etching, resist ashing, wafer cleaning, and oxidation. In this work, we investigate the impact of these processes on the polycrystalline Si 1 - x Ge x profile and the critical dimension (CD) of the gate electrode. The process improvements and an integration scheme using an oxide liner are presented to minimize the profile and CD variations introduced by the fabrication processes.


Archive | 2008

Application of gate edge liner to maintain gate length CD in a replacement gate transistor flow

Richard J. Carter; Wai Lo; Sey-Shing Sun; Hong Lin; Verne Hornback


Archive | 2003

High-k dielectric bird's beak optimizations using in-situ O2 plasma oxidation

Hong Lin; Shiqun Gu; Wai Lo; Jim Elmer


Archive | 2005

Superconductor wires for back end interconnects

Shiqun Gu; Wai Lo; Hong Lin


Archive | 2005

Process and apparatus for simultaneous light and radical surface treatment of integrated circuit structure

Shiqun Gu; Wai Lo; Hong Lin


Archive | 2003

Selective high k dielectrics removal

Wai Lo; Hong Lin; Shiqun Gu; James R. B. Elmer


Archive | 2004

Plasma removal of high k metal oxide

Hong Lin; Shiqun Gu; Wai Lo; James R. B. Elmer


Archive | 2006

Incorporating dopants to enhance the dielectric properties of metal silicates

Wai Lo; Verne Hornback; Wilbur G. Catabay; Wei-jen Hsia; Sey-Shing Sun


Archive | 2004

Interconnect dielectric tuning

Wai Lo; Hong Lin; Shiqun Gu; Wilbur G. Catabay; Zhihai Wang; Wei-jen Hsia

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