Vibhu Sharma

A 4.4 pJ/Access 80 MHz, 128 kbit Variability Resilient SRAM With Multi-Sized Sense Amplifier Redundancy

An ultra low energy, 128 kbit 6T SRAM in 90 nm LP CMOS with energy consumption of 4.4 pJ/access, operating at 80 MHz for the wireless sensor applications is developed. The variability resilient and low power techniques developed include innovation in the local architecture with the use of local read/write assist circuitry. The energy-efficient hierarchical bit-lines structure includes low swing global bit-lines and VDD/2 pre-charged short local bit-lines. The innovative Multi-Sized SA redundancy (MS-SA-R) calibration technique for the global read sense amplifiers of the SRAM not only adds to the variability resilience but also yields maximum energy reduction compared with existing calibration techniques.

8T SRAM with Mimicked Negative Bit-lines and Charge Limited Sequential sense amplifier for wireless sensor nodes

This design sets a record low energy consumption (average RD/WR) of 2.65pJ/access for a 64kbit embedded SRAM operating at 90MHz in 65nm LP CMOS. This low energy and variability resilient SRAM macro ensures write-ability with an innovative Mimicked Negative Bit-line technique. The novel low energy Charge Limited Sequential sense amplifier consumes 11.36fJ/decision and obtains σVoffset of 14.297mV without requiring calibration.

A 4.4pJ/access 80MHz, 2K word } 64b memory with write masking feature and variability resilient multi-sized sense amplifier redundancy for wireless sensor nodes applications

A Variability resilient 128kbit 6T SRAM with energy consumption of 4.4pJ/access, operating at 80MHz for wireless sensor applications is developed in 90nm LP CMOS. The techniques developed include novelty in the local architecture with local read/write assist circuitry. VDD/2 pre-charged short local bit-lines with local sense amplifier enables charge re-cycling and gated read buffers eliminates bit-line leakage The multi-sized sense amplifier redundancy used for global sense amplifiers ensures variability resilient low energy consumption read operation.

SRAM Design for Wireless Sensor Networks

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SRAM Bit Cell Optimization

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Ultra low power litho friendly local assist circuitry for variability resilient 8T SRAM

This chapter discusses different SRAM bit cell topologies. This chapter first provides an overview of the conventional SRAM 6T cell and its limitations. Then different SRAM cell topologies are discussed which offers better stability margins compared to 6T SRAM cell. Different cell topologies discussed are broadly categorized as 7T, 8T, and 10T. It also classifies SRAM cells based on single ended and differential sensing. Finally, the chapter concludes with a summary of different SRAM cells topologies.

Adaptive Voltage Optimization Techniques: Low Voltage SRAM Operation

This paper presents litho friendly circuit techniques for variability resilient low power 8T SRAM. The new local assist circuitry achieves a state-of-the-art low energy and variability resilient WRITE operation and improves the degraded access speed of SRAM cells at low voltages. Differential VSS bias increases the variability resilience. The physical regularity in the layout of local assist circuitry enables litho optimization thereby reducing the area overhead associated with existing local assist techniques. Statistical simulations in 40nm LP CMOS technology reveals 10x reduction in WRITE energy consumption, 103x reduction in write failures, 6.5x improvement in read access time and 31% reduction in the area overhead.

Variation Tolerant Low Power Sense Amplifiers

The minimum supply voltage for SRAM cell is limited by write failures (write-ability) or read disturb failures (cell stability). In the previous chapter, various SRAM cells are discussed which offer better variability resilience compared to the SRAM 6T cell and enable low VDD operation. SRAM 6T cell functionality is highly dependent on the supply voltage. The voltage optimization can impact the write failures and the read disturb failures significantly. In this chapter, dynamic voltage optimization techniques, are studied for realizing low VDD operation with the conventional SRAM 6T cell while maintaining sufficient READ/WRITE margins.

SRAM Energy Reduction Techniques

This chapter describes the READ sense amplifier of the memory. It discusses the fundamental limitation on the SA performance, especially for the memories in deep submicron technologies. It covers various calibration based sense amplifier design techniques. With the practical implementation details for Multi-sized SA redundancy. And comparison of the various calibration based techniques. Then a charge limited sequential sensing concept is discussed. Finally the design and implementation details of a calibration free sense amplifier based on the charge limited sequential sensing is provided.

Circuit Techniques to Assist SRAM Cell: Local Assist Circuitry

The memories are the most vulnerable to ever increasing process variations in advanced technology nodes as discussed in previous chapters. SRAM bit cell functional parameter degradation due to increasing variability and decreasing power supply is of utmost concern. The increasing intra die variations degrade cell read current, read SNM, and the write margin of the SRAM cell. The SRAM cell design, voltage optimization, and circuit design techniques are required which enhances the operating margin of SRAM and also reduces the energy consumption. The previous chapters discuss only about enhancing the operating margins of SRAM. The energy consumption perspective was not covered. This chapter discusses about various circuit design techniques which result in ultra low energy SRAM operation.