Stefan Cosemans

Dynamic ‘hour glass’ model for SET and RESET in HfO 2 RRAM

An analytic dynamic hour glass model for HfO2 RRAM is demonstrated, describing the reset as a dynamic equilibrium process and the set as a constriction growth limited by ion mobility and current compliance. The dependence on time, voltage and forming conditions is in good constriction growth agreement with experiments. Since the model is fully analytical, it can be implemented in a circuit simulator.

A 3.6 pJ/Access 480 MHz, 128 kb On-Chip SRAM With 850 MHz Boost Mode in 90 nm CMOS With Tunable Sense Amplifiers

An extremely low energy per operation, single cycle 32 bit/word, 128 kb SRAM is fabricated in 90 nm CMOS. In the 850 MHz boost mode, total energy consumption is 8.4 pJ/access. This reduces to 3.6 pJ/access in the normal 480 MHz mode and bottoms out at a very aggressive 2.7 pJ/access in the 240 MHz low power mode. Several techniques were combined to obtain these performance numbers. Short buffered local bit lines reduce the impact of the cell read current on memory delay. Extended global bitlines are used which improves delay and energy consumption and which reduces the number of sense amplifiers in the memory to 32. Cell stability and speed issues are avoided by applying selective voltage scaling. Novel, digitally tunable sense amplifiers and a tunable timing circuit cope gracefully with the stochastic variations in the periphery.

A Low-Power Embedded SRAM for Wireless Applications

This paper introduces a novel ultra-low-power SRAM. A large power reduction is obtained by the use of four new techniques that allow for a wider and better trade-off between area, delay and active and passive energy consumption for low-power embedded SRAMs. The design targets wireless applications that require a moderate performance at an ultra-low-power consumption. The implemented design techniques consist of a more efficient memory databus, the exploitation of the dynamic read stability of SRAM cells, a new low-swing write technique and a distributed decoder. An 8-KB 5T SRAM was fabricated in a 0.18-mum technology. The measurement results confirm the feasibility and the usefulness of the proposed techniques. A reduction of active power consumption with a factor of 2 is reported as compared to the current state of the art. The results are generalized towards a 32-KB SRAM.

Spin-Hall assisted magnetic random access memory

We propose a write scheme for perpendicular spin-transfer torque magnetoresistive random-access memory that significantly reduces the required tunnel current density and write energy. A sub-nanosecond in-plane polarized spin current pulse is generated using the spin-Hall effect, disturbing the stable magnetic state. Subsequent switching using out-of-plane polarized spin current becomes highly efficient. Through evaluation of the Landau-Lifshitz-Gilbert equation, we quantitatively assess the viability of this write scheme for a wide range of system parameters. A typical example shows an eight-fold reduction in tunnel current density, corresponding to a fifty-fold reduction in write energy, while maintaining a 1 ns write time.

A 3.6pJ/access 480MHz, 128Kbit on-Chip SRAM with 850MHz boost mode in 90nm CMOS with tunable sense amplifiers to cope with variability

An extremely low energy/operation, single cycle 32 bit/word, 128 Kbit SRAM is fabricated in 90 nm CMOS. In the 850 MHz boost mode, energy consumption is 8.4 pJ/access. This reduces to 3.6 pJ/access in the normal 480 MHz mode and bottoms out at a very aggressive 2.7 pJ/access in the 240 MHz low power mode. This performance is obtained using novel, digitally tunable sense amplifiers and a tunable timing circuit that cope gracefully with the stochastic variations in the periphery.

Analysis of vertical cross-point resistive memory (VRRAM) for 3D RRAM design

An analysis of 3D VRRAM is presented, taking into account read/write margin, leakage and power consumption. The results give guidelines for array dimensioning (number of layers / in plane array size) and bias conditions. The read margin is more sensitive to the number of layers than the in plane array size in the matrix, while a tradeoff is found between read margin and total leakage/power. Optimized write bias conditions are determined, which improve both write margin and power consumption as compared to the results using the standard bias schemes. A comparison shows that VRRAM is more promising than stacked 3D RRAM, not only from a cost perspective, but also provides better electrical behavior, both for read and write.

A 4.4 pJ/Access 80 MHz, 128 kbit Variability Resilient SRAM With Multi-Sized Sense Amplifier Redundancy

An ultra low energy, 128 kbit 6T SRAM in 90 nm LP CMOS with energy consumption of 4.4 pJ/access, operating at 80 MHz for the wireless sensor applications is developed. The variability resilient and low power techniques developed include innovation in the local architecture with the use of local read/write assist circuitry. The energy-efficient hierarchical bit-lines structure includes low swing global bit-lines and VDD/2 pre-charged short local bit-lines. The innovative Multi-Sized SA redundancy (MS-SA-R) calibration technique for the global read sense amplifiers of the SRAM not only adds to the variability resilience but also yields maximum energy reduction compared with existing calibration techniques.

One-Selector One-Resistor Cross-Point Array With Threshold Switching Selector

This paper investigates the impact of threshold switching (TS) selector characteristics on the one-selector one-resistor (1S1R) cross-point array performance. TS selector parameter requirements are extracted for 1 Mb array, considering 1S, 1R cell compatibility, read/write margin, and power consumption constraints. The SPICE simulation results show that the threshold voltage (Vth) and the ON-state resistance (Rs) are important selector parameters. Low Vth eliminates 1R disturb issue during the read operation, but this comes at the expense of losing full cell nonlinearity (NL) during the write operation. Increase of Vth and Rs improves the full cell NL and alleviate read disturb issue. However, these reduce 1S1R read window and additional voltages are required for both read and write operations. Compared with selector with nonabrupt current-voltage (I-V) characteristics, the TS selector is more favorable for the low-voltage operation. Finally, different reported TS selectors are evaluated, and the improvement directions are suggested.

High-drive current (>1MA/cm 2 ) and highly nonlinear (>10 3 ) TiN/amorphous-Silicon/TiN scalable bidirectional selector with excellent reliability and its variability impact on the 1S1R array performance

An optimized TiN/amorphous-Silicon/TiN (MSM) two-terminal bidirectional selector is proposed for high density RRAM arrays. The devices show superior performance with high drive current exceeding 1MA/cm2 and half-bias nonlinearity of 1500. Excellent reliability is fully demonstrated on 40nm-size crossbar structures, with statistical ability to withstand bipolar cycling of over 106 cycles at drive current conditions and thermal stability of device operation exceeding 3hours at 125°C. Furthermore, for the first time, we address the impact of selector variability in a 1S1R memory array, by including circuit simulations in a Monte Carlo loop and point out the importance of selector variability for the low resistive state and its implications on the read margin and power consumption.

A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, ultra low leakage power memory using dynamic cell stability and a dual swing data link

This paper presents a 65nm, 256 kbit SRAM memory which achieves both ultra low leakage power and very low active energy consumption at a speed of 850 MHz. Used techniques include divided word and bitlines, local write sense amplifiers, dynamic cell stability and a distributed decoder. In addition, three novel techniques are proposed which decrease power consumption even further. High threshold voltage cells reduce leakage and improve stability. Dual swing signalling on the global bitlines reduces energy without compromising robustness. The decoder uses a new type of dynamic gate to increase speed. The design was fabricated in a low power 65nm CMOS process. Measured performance for this 256 kbit SRAM with 32 bit wordlength is 4.3pJ per access and 25.2 μW leakage power at a speed of 850 MHz.