Vicenc Almenar

The use of CORDIC in software defined radios: a tutorial

CORDIC is a versatile algorithm widely used for VLSI implementation of digital signal processing applications. This article presents a tutorial of how to use CORDIC to implement different communication subsystems that can be found in a software defined radio. Specifically, it shows how to use CORDIC to implement direct digital synthesizers, AM, PM, and FM analog modulators and ASK, PSK and FSK modulators, up-/down-converters of in-phase and quadrature signals, full mixers for complex signals, and phase detection for synchronizers. The article also shows some tricks to efficiently implement the algorithm

Diversity techniques for OFDM based WLAN systems

This paper presents different spatial diversity techniques that can be employed in an OFDM based WLAN system to improve the system performance. We present some results obtained by simulation when a HIPERLAN/2 transceiver is employed.

FPGA implementation of an IF transceiver for OFDM-based WLAN

The paper deals with the design and implementation on FPGA of an intermediate frequency transceiver for OFDM-based WLAN. The circuit has been particularized for the HIPERLAN/2 standard, but most of the work can be generalized to IEEE 802.11a/g standards. The system is composed of three main blocks (autocorrelator, CORDIC, and FFT processor) that are used in different time intervals to perform all the required operations. The autocorrelator is used for frame detection and carrier frequency offset estimation. The CORDIC is reused to estimate frequency offset, to compensate that frequency and to calculate the division in the channel estimation stage. Finally, the FFT/IFFT processor also uses its complex-number multiplier to perform the channel compensation of the received OFDM symbols. The whole IF transceiver fits in a low cost FPGA, an XC3S400-4 Spartan III device.

FFT Spectrum Analyzer Project for Teaching Digital Signal Processing With FPGA Devices

This paper presents a course on digital signal processing with field-programmable gate arrays (FPGA) devices. The course integrates two separate disciplines, digital signal processing (DSP) and very large scale integration (VLSI) design, and focuses on the development of a sophisticated DSP design from simulation to fixed-point implementation. The structure and methodology used in the proposed course are oriented to the design and implementation of an fast Fourier transform (FFT) spectrum analyzer. This application covers most topics included in a DSP course and gives better results that those obtained with typical courses performing independent multiple simple experiments. The project is divided into modules that show specific learning necessities and determine the course contents and organization. Each laboratory part is dedicated to design and implements the block of the analyzer related to the theoretical content presented in the class. At the end of the course the students have designed all the pieces in the DSP project and have completed and verified the system. The used methodology enables students and engineers to understand and develop complex fixed-point applications, looking for the best signal processing algorithms on hardware implementations, and also results in more motivated and active students.

Fully Parallel GPU Implementation of a Fixed-Complexity Soft-Output MIMO Detector

Multicore and graphic processing units (GPUs) can be combined to efficiently implement signal-processing algorithms for communication systems, due to their parallel processing capabilities. This paper proposes a fully parallel fixed-complexity soft-output detector, which is suitable for GPU implementation and allows a considerable decrease in the computational time required for the data detection stage in multiple-input-multiple-output (MIMO) systems. A novel channel matrix preprocessing stage, based on column-norm ordering, is developed to efficiently match the multicore architecture. The throughput of the implementation is shown to outperform other recent implementations and to support some of the configurations in the long-term evolution (LTE) standard.

Combined K-Best sphere decoder based on the channel matrix condition number

It is known that sphere decoding (SD) methods can provide maximum-likelihood (ML) detection over Gaussian MIMO channels with lower complexity than the exhaustive search. Channel matrix condition number represents an important influence on the performance of usual detectors. Throughout this paper, two particular cases of a SD method called K-Best carry out a combined detection in order to reduce the computational complexity with predictable performance degradation. Algorithm selection is based on channel matrix condition number thresholding. K-Best is a suboptimal SD algorithm for finding the ML solution of a detection problem. It is based on a fixed complexity tree search, set by a parameter called k. The proposed receiver makes use of a low value of k while working with well-conditioned channels and switches to a higher value of k whether the channel gets worse. It is also presented practical algorithms for finding the 1-norm condition number of a given channel matrix and the condition number threshold selection. Finally an algorithm variant that switches between an ML SD and a linear detector is also evaluated.

Distance Estimation System Based on ZigBee

Many systems exist (TOA, AOA, RSSI) that can be used with diverse technologies (ultrasounds, infrared, Bluetooth, 802,11...) for the indoor location. In this article we chose to apply TOA on a network ZigBee, to be able to add a useful functionality for other applications in an existing network and, in addition, presents characteristics of minimum consumption and low cost. The results that we obtain are promising, because we obtain a precision near the meter in 90% of the cases.

Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor

This paper proposes a low-complexity min-sum algorithm for decoding low-density parity-check codes. It is an improved version of the single-minimum algorithm where the two-minimum calculation is replaced by one minimum calculation and a second minimum emulation. In the proposed one, variable correction factors that depend on the iteration number are introduced and the second minimum emulation is simplified, reducing by this way the decoder complexity. This proposal improves the performance of the single-minimum algorithm, approaching to the normalized min-sum performance in the water-fall region. Also, the error-floor region is analyzed for the code of the IEEE 802.3an standard showing that the trapping sets are decoded due to a slow down of the convergence of the algorithm. An error-floor free operation below BER=10-15 is shown for this code by means of a field-programmable gate array (FPGA)-based hardware emulator. A layered decoder is implemented in a 90-nm CMOS technology achieving 12.8 Gbps with an area of 3.84 mm2.

FPGA implementation of an OFDM-based WLAN receiver

This paper deals with the design and implementation on FPGA of a receiver for OFDM-based WLAN. The circuit is particularized for IEEE 802.11a/g standards. The system includes frame detection, time and frequency synchronization, demodulation, equalization and phase tracking. The algorithms to be implemented for each task are selected taking into account performance, hardware cost and latency. Also, a fixed point analysis is made for each algorithm. Our objective is to maintain the PER loss below 0.5dB for a PER=10^-^2, 64-QAM and error correction. The whole system is composed of two main blocks (correlator and CORDIC) that are reused in different time intervals to perform all the necessary operations, so the required hardware resources are minimized. To verify it, the receiver is physically implemented and tested.

Tridimensional block multiword LDPC decoding on GPUs

In this paper, we describe a parallel algorithm for LDPC (Low Density Parity Check codes) decoding on a GPU (Graphics Processing Unit) using CUDA (Compute Unified Device Architecture). The strategy of the kernel grid and block design is shown and the multiword decoding operation is described using tridimensional blocks. The performance (speedup) of the proposed parallel algorithm is slightly better than the performance found in the literature when this is relatively good, and shows a great improvement in those cases with previously reported moderate or bad performance.