V. Torres

The use of CORDIC in software defined radios: a tutorial

CORDIC is a versatile algorithm widely used for VLSI implementation of digital signal processing applications. This article presents a tutorial of how to use CORDIC to implement different communication subsystems that can be found in a software defined radio. Specifically, it shows how to use CORDIC to implement direct digital synthesizers, AM, PM, and FM analog modulators and ASK, PSK and FSK modulators, up-/down-converters of in-phase and quadrature signals, full mixers for complex signals, and phase detection for synchronizers. The article also shows some tricks to efficiently implement the algorithm

FFT Spectrum Analyzer Project for Teaching Digital Signal Processing With FPGA Devices

This paper presents a course on digital signal processing with field-programmable gate arrays (FPGA) devices. The course integrates two separate disciplines, digital signal processing (DSP) and very large scale integration (VLSI) design, and focuses on the development of a sophisticated DSP design from simulation to fixed-point implementation. The structure and methodology used in the proposed course are oriented to the design and implementation of an fast Fourier transform (FFT) spectrum analyzer. This application covers most topics included in a DSP course and gives better results that those obtained with typical courses performing independent multiple simple experiments. The project is divided into modules that show specific learning necessities and determine the course contents and organization. Each laboratory part is dedicated to design and implements the block of the analyzer related to the theoretical content presented in the class. At the end of the course the students have designed all the pieces in the DSP project and have completed and verified the system. The used methodology enables students and engineers to understand and develop complex fixed-point applications, looking for the best signal processing algorithms on hardware implementations, and also results in more motivated and active students.

FPGA-implementation of atan(Y/X) based on logarithmic transformation and LUT-based techniques

This paper presents an architecture for the computation of the atan(Y/X) operation suitable for broadband communications systems where a throughput between 20 and 40MHz is required. The proposed architecture implements a division operation of two inputs by means of a logarithmic transformation, in which the division can be performed with a subtraction. A combination of non-uniform segmentation and multipartite LUT technique is proposed for the arctangent of the logarithm approximation. The architecture was implemented in a Xilinx FPGA device achieving higher throughput than the approach based on CORDIC algorithm and lower area than previous LUT-based approaches.

Reduced-Complexity Min-Sum Algorithm for Decoding LDPC Codes With Low Error-Floor

This paper proposes a low-complexity min-sum algorithm for decoding low-density parity-check codes. It is an improved version of the single-minimum algorithm where the two-minimum calculation is replaced by one minimum calculation and a second minimum emulation. In the proposed one, variable correction factors that depend on the iteration number are introduced and the second minimum emulation is simplified, reducing by this way the decoder complexity. This proposal improves the performance of the single-minimum algorithm, approaching to the normalized min-sum performance in the water-fall region. Also, the error-floor region is analyzed for the code of the IEEE 802.3an standard showing that the trapping sets are decoded due to a slow down of the convergence of the algorithm. An error-floor free operation below BER=10-15 is shown for this code by means of a field-programmable gate array (FPGA)-based hardware emulator. A layered decoder is implemented in a 90-nm CMOS technology achieving 12.8 Gbps with an area of 3.84 mm2.

Hardware Architecture of a Gaussian Noise Generator Based on the Inversion Method

In this brief, we present a hardware-based Gaussian noise generator (GNG) with low hardware cost, high generation rate, and high Gaussian tail accuracy. The proposed generator is based on a piecewise polynomial approximation of the inverse cumulative distribution function (ICDF). We propose to avoid the area-demanding barrel-shifter of the ICDF approximation by means of creating a new uniform random sequence from the uniform random number generator output. The GNG architecture has been implemented in field-programmable gate array devices, and the implementation results are compared with other published designs, achieving a higher deviation with fewer hardware resources. Our GNG generates 242 Msps of random noise and achieves a tail of 13.1

Fully-parallel LUT-based (2048,1723) LDPC code decoder for FPGA

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Scheme for Reducing the Storage Requirements of FFT Twiddle Factors on FPGAs

with 442 slices, two multipliers, and two Block-RAM of a Virtex-II device. The generator output successfully passed commonly used statistical tests.

High-throughput FPGA-based emulator for structured LDPC codes

A good trade-off between performance and complexity is achieved if the min-sum algorithm with 2-bit non-uniform quantization is used to decode Low-Density Parity-Check codes. This paper proposes a method to design Variable Node Update (VNU) units based on Look-up tables suitable to design decoders for this algorithm. The method has been developed for the (2048,1723) LDPC code of the IEEE 802.3an standard and fully-parallel architectures have been implemented in a FPGA device. The results show that with the proposed method 35% area saving is achieved with respect to the use of the conventional VNU units.

Design of Power and Area Efficient Digital Down-converters for Broadband Communications Systems

A scheme for reducing the hardware resources to implement on LUT-based FPGA devices the twiddle factors required in Fast Fourier Transform (FFT) processors is presented. The proposed scheme reduces the number of embedded block RAM for large FFTs and the number of slices for FFT lengths higher than 128 points. Results are given for Xilinx devices, but they can be generalized for other advanced LUT-based devices like ALTERA Stratix.

Design of high performance timing recovery loops for communication applications

FPGA-based emulators are used to evaluate the LDPC codes performance at low bit error rates (BER). We propose an emulator for structured LDPC codes that takes advantage of the early termination in high signal-to-noise ratios (SNRs), where most of the received frames can be decoded in one iteration. Moreover, the data generation (received frames) was parallelised to avoid bottlenecks when the decoder throughput is maximum. The emulator was implemented on a Virtex-6 device a (2048,1723) RS-Based LDPC code using the normalised-MS algorithm, achieving an average throughput of 1.35 Gbps with a single core and, 5.7 Gbps with 4 cores in a single FPGA device. The achieved throughput is 4 times faster than the state-of-the-art FPGA emulators in the literature.