María José Canet

FPGA implementation of an IF transceiver for OFDM-based WLAN

The paper deals with the design and implementation on FPGA of an intermediate frequency transceiver for OFDM-based WLAN. The circuit has been particularized for the HIPERLAN/2 standard, but most of the work can be generalized to IEEE 802.11a/g standards. The system is composed of three main blocks (autocorrelator, CORDIC, and FFT processor) that are used in different time intervals to perform all the required operations. The autocorrelator is used for frame detection and carrier frequency offset estimation. The CORDIC is reused to estimate frequency offset, to compensate that frequency and to calculate the division in the channel estimation stage. Finally, the FFT/IFFT processor also uses its complex-number multiplier to perform the channel compensation of the received OFDM symbols. The whole IF transceiver fits in a low cost FPGA, an XC3S400-4 Spartan III device.

FPGA implementation of an OFDM-based WLAN receiver

This paper deals with the design and implementation on FPGA of a receiver for OFDM-based WLAN. The circuit is particularized for IEEE 802.11a/g standards. The system includes frame detection, time and frequency synchronization, demodulation, equalization and phase tracking. The algorithms to be implemented for each task are selected taking into account performance, hardware cost and latency. Also, a fixed point analysis is made for each algorithm. Our objective is to maintain the PER loss below 0.5dB for a PER=10^-^2, 64-QAM and error correction. The whole system is composed of two main blocks (correlator and CORDIC) that are reused in different time intervals to perform all the necessary operations, so the required hardware resources are minimized. To verify it, the receiver is physically implemented and tested.

Serial Symbol-Reliability Based Algorithm for Decoding Non-Binary LDPC Codes

A symbol-reliability based decoding algorithm with serial schedule for non-binary low-density parity-check (LDPC) codes is presented. Performance results, together with implementation complexity analysis, are provided for different sample codes. The proposed algorithm achieves a similar gain to the min- max algorithm for codes with column weight dv ≥ 6, with lower complexity than previous symbol-reliability based algorithms.

Time Synchronization for the IEEE 802.11a/g WLAN Standard

In this paper a time synchronization algorithm for IEEE 802.11a/g OFDM-WLAN standard is presented and some modifications are proposed to simplify its implementation without sacrifice its performance. To evaluate its feasibility this algorithm is compared with others found in the literature. The comparison of performance has been carried out by simulation in multipath channels, at low signal to noise ratios and with carrier frequency offset. It is shown that the proposed solution has a better performance and a lower computational cost.

Nonbinary LDPC Decoder Based on Simplified Enhanced Generalized Bit-Flipping Algorithm

A simplified version of the enhanced serial generalized bit-flipping algorithm is proposed in this brief. This new algorithm reduces the quantity of information that is stored with a negligible performance loss of 0.05 dB compared with previous proposals. In addition, the algorithm allows us not only to save memory, but also to reduce the number of arithmetic resources needed. In addition, a new initialization of the algorithm avoids using techniques to control data growth without any performance degradation, reduces routing, increasing the maximum frequency achievable, and saves logic. The decoder derived from the simplified algorithm requires almost half the area of previous architectures, with a throughput of 716 Mbps on a 90-nm CMOS process for the (837, 723) nonbinary code over GF(32) at ten iterations.

Decoder for an enhanced serial generalized bit flipping algorithm

An enhanced serial generalized bit-flipping algorithm is proposed in this paper. This new algorithm includes method to compute the extrinsic information during all the iterations, improving the performance of the algorithm in the waterfall region compared to the direct serial description. In addition, the algorithm allow us to reduce the storage resources the derived architecture. The decoder was implemented on a Virtex-VI FPGA device for the (837,723) non-binary code over GF(25), achieving 439 Mbps at 10 iterations.

High-Throughput Interpolator Architecture for Low-Complexity Chase Decoding of RS Codes

In this paper, a high-throughput interpolator architecture for soft-decision decoding of Reed-Solomon (RS) codes based on low-complexity chase (LCC) decoding is presented. We have formulated a modified form of the Nielsons interpolation algorithm, using some typical features of LCC decoding. The proposed algorithm works with a different scheduling, takes care of the limited growth of the polynomials, and shares the common interpolation points, for reducing the latency of interpolation. Based on the proposed modified Nielsons algorithm we have derived a low-latency architecture to reduce the overall latency of the whole LCC decoder. An efficiency of at least 39%, in terms of area-delay product, has been achieved by an LCC decoder, by using the proposed interpolator architecture, over the best of the previously reported architectures for an RS(255,239) code with eight test vectors. We have implemented the proposed interpolator in a Virtex-II FPGA device, which provides 914 Mb/s of throughput using 806 slices.

A common FPGA based synchronizer architecture for Hiperlan/2 and IEEE 802.11a WLAN systems

This paper deals with the design and implementation of a frame, time and frequency synchronizer for both Hiperlan/2 and IEEE 802.11a WLAN standards. In a packet oriented system, to perform a quick and correct synchronization it is critical to avoid severe bit error rate degradation. So, the design of this subsystem is one of the most challenging tasks to be done in the implementation of a transceiver. In this paper we give practical solutions to the hardware design problems that arise when the synchronization algorithm is turned into a digital circuit. We evaluate the fixed-point realization of the synchronization algorithm and introduce some simplifications to reduce, as much as possible, the cost in area of the circuit without losing its performance.

Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min–Max Algorithm

Nonbinary LDPC codes outperform their binary counterparts in different scenarios. However, they require a considerable increase in complexity, especially in the check-node (CN) processor, for high-order Galois fields (GFs) higher than GF(16). To overcome this drawback, we propose an approximation for the trellis min-max algorithm that allows us to reduce the number of exchanged messages between the CN and the variable node compared with previous proposals from the literature. On the other hand, we reduce the complexity in the CN processor, keeping the parallel computation of messages. We implemented a layered scheduled decoder, based on this algorithm, in a 90-nm CMOS technology for the (837, 723) NB-LDPC code over GF(32) and the (1536, 1344) over GF(64), achieving an area saving of 16% and 36% for the CN and 10% and 12% for the whole decoder, respectively. The throughput is 1.07 and 1.26 Gb/s, which outperforms the state of the art of high-rate decoders with the high GF order from the literature.

Low Complexity Time Synchronization Algorithm for OFDM Systems with Repetitive Preambles

In this paper, a new time synchronization algorithm for OFDM systems with repetitive preamble is proposed. This algorithm makes use of coarse and fine time estimation; the fine time estimation is performed using a cross-correlation similar to previous proposals in the literature, whereas the coarse time estimation is made using a new metric and an iterative search of the last sample of the repetitive preamble. A complete analysis of the new metric is included, as well as a wide performance comparison, for multipath channel and carrier frequency offset, with the main time synchronization algorithms found in the literature. Finally, the complexity of the VLSI implementation of this proposal is discussed.