Victor Liang

On the RF Extrinsic Resistance Extraction for Partially-Depleted SOI MOSFETs

We have investigated the radio frequency (RF) extrinsic resistance extraction for partially-depleted (PD) silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistors (MOSFETs). Although the thick buried oxide in SOI devices can block the substrate coupling, the SOI neutral-body coupling effect is significant for RF applications. An equivalent circuit considering this effect has been proposed. Based on this equivalent circuit, a new model capturing the frequency dependence of extrinsic resistances has been derived. After considering the impact of quasi-neutral body, we have developed a physically accurate RF extrinsic resistance extraction methodology for PD SOI MOSFETs

Linearity and power characteristics of SiGe HBTs at high temperatures for RF applications

In this paper, the power gain, power-added efficiency (PAE) and linearity of power SiGe heterojunction-bipolar transistors at various temperatures have been presented. The power characteristics were measured using a two-tone load-pull system. For transistors biased with fixed base voltage, the small-signal power gain and PAE of the devices increase with increasing temperature at low base voltages, while they decrease at high base voltages. Besides, the linearity is improved at high temperature for all voltage biases. However, for devices with fixed collector current, the small-signal power gain, PAE, and linearity are nearly unchanged with temperature. The temperature dependence of power and linearity characteristics can be understood by analyzing the cutoff frequency, the collector current, Kirk effect and nonlinearities of transconductance at different temperatures.

Hot-carrier induced degradations on RF power characteristics of SiGe heterojunction bipolar transistors

Hot-carrier (HC) effects on high-frequency and RF power characteristics of Si/SiGe HBTs are investigated in this paper. By using the two-tone load-pull measurement, we find that not only the cutoff frequency, but also the output power performances of Si/SiGe HBTs are suffered by the HC stress. In this work, S-parameters and intrinsic elements of an equivalent hybrid-/spl pi/ model were used to validate the HC effects on high-frequency characteristics. With different bias conditions, the degradations of cutoff frequency, power gain, and linearity are found to be worse under constant base-current measurement than that under constant collector-current measurement. The HC-induced degradations on the current gain, transconductance, and ideality-factor of base and collector currents are analyzed to explain the experimental observations.

Design for Integration of RF Power Transistors in 0.13 μm Advanced CMOS Technology

An RF power MOSFET was proposed and manufactured in a standard 0.13 μm CMOS technology. Without adding additional masks, cost and process, the breakdown voltage can be improved by using the N-well and shallow-trench-isolation processes to form a drift n- region. The breakdown voltage was 4.3 V at gate bias of 1.2 V. The cutoff frequency and maximum oscillation frequency were 68 GHz and 87 GHz, respectively. In addition, the power gain, output power and power-added efficiency were 16.8 dB, 15.9 dBm and 43.5%, respectively, at 2.4 GHz. Good RF linearity also addressed OIP3 of 28.6 dBm. The presented RF power transistor is cost effectively and can be applied into the power amplifier integration for RF SoC.

Impact of hot carrier stress on RF power characteristics of MOSFETs

This paper investigates hot-carrier (HC) effects on the RF power and linearity characteristics of MOS transistors using load-pull measurement. We found that the RF power characteristics are affected by the HC stress, and the linearity of MOS transistors is clearly degraded after HC stress at constant gate voltage measurement. However, at high gate voltage bias, the HC-induced power degradation is much reduced compared with that under low gate voltage regimes. In addition, HC effects on linearity can be softened by biasing the transistor at constant drain currents. These experimental observations can be explained by the change of threshold voltage, transconductance, subthreshold swing, and mobility degradation coefficient under HC stress.

Novel Pseudo-Drain (PD) RF power cell in 0.13 um CMOS technology

This paper proposes a cost-effective RF power cell manufactured in an advanced 0.13 um CMOS technology. Without adding additional masks, cost, and process, the power performance can be improved just by using the standard N-well and shallow-trench-isolation processes to form a higher resistive region. This ldquoPseudo-Drainrdquo structure increases the breakdown voltage to more than 4.3V and is higher than the value of 2.5V of the standard 0.13 um core-MOS transistor. This transistor exhibits a high fTtimesBVDS product of 352 for CMOS power FETs. Cutoff frequency and maximum oscillation frequency of 83 GHz and 124 GHz were achieved at a drain bias of 1.2V, respectively; while the maximum power gain, output power and power-added efficiency were 25.6 dB, 19 dBm, and 55%, respectively. Good RF linearity and noise figure were also obtained, as demonstrated by an OIP3 and NFmin of 28.32 dBm and 0.4 dB. The presented RF power transistor is cost effective and can be used for power amplifier integration in RF-CMOS SOC.

RF Small-Signal and Noise Modeling for SOI Dynamic Threshold Voltage MOSFETs

Phone: +886-3-5726100 Fax: +886-3-5733795 E-mail: scwang@ndl.org.tw Department of Electronics Engineering, National Chiao Tung University, 1001 Ta-Hsueh Rd., Hsinchu, Taiwan, R.O.C. 2 National Nano Device Laboratories, No. 26, Prosperity Rd. 1, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C. United Microelectronics Corporation, No. 3, Li-Hisn Rd. 2, Science-Based Industrial Park, Hsinchu, Taiwan, R.O.C.

Radio-Frequency Silicon-on-Insulator Modeling Considering the Neutral-Body Effect

This paper presents small-signal modeling for state-of-the-art radio-frequency (RF) silicon-on-insulator (SOI) metal–oxide–semiconductor field effect transistors (MOSFETs). Especially, we have incorporated the neutral-body effect in our RF SOI model. This effect is significant in both RF extrinsic and intrinsic modeling stages. In addition, we have developed a physically-accurate parameter extraction method based on our analytical expressions. Our modeling results agree well with the measured data and can capture the frequency dependences of both output conductance and capacitance in the GHz frequency region. The anomalous S22 and S21 behaviors as well as the output conductance rising effect observed in our measurements can be predicted and described using the proposed model.

RF Extrinsic Resistance Extraction Considering Neutral-Body Effect for Partially-Depleted SOI MOSFETs

The extraction of extrinsic resistances is essential to RF CMOS modeling. In this work, we investigate the extrinsic resistance extraction for PD SOI MOSFETs. We have shown that, for RF SOI MOSFETs, the coupling path between the source and drain terminals through the neutral-body region beneath the gate-oxide layer makes the resistance expressions behave frequency-dependently. After taking this effect into account, we develop a physical RF extrinsic resistance extraction methodology for PD SOI MOSFETs

Effects of hot carrier stress and oxide breakdown on RF characteristics of MOSFETs

Effects of hot carrier stress and oxide breakdown on the main figures-of-merit of RF MOSFETs are examined in this paper. We found that the degradations of cutoff frequency and power performance after hot carrier stress are larger than that after oxide breakdown. However, the minimum noise figure degradation is more significant after oxide breakdown. Those observations are important and should be concerned when designing an RF front-end circuit.