Victor Sonnenberg

Analysis of transition region and accumulation layer effect in the subthreshold slope in SOI nMOSFETs and their influences on the interface trap density extraction

Abstract Measurements were performed in thin film silicon on insulator (SOI) nMOSFETs and it was observed a transition region in the subthreshold slope, larger than the theoretically expected, when the back interface (silicon film/buried oxide) changes from accumulation to depletion. Also, it was observed a non-constant plateau in the subthreshold slope when the back interface is accumulated. MEDICI numerical bidimensional simulations were performed in order to analyze this transition region. It was verified that there is a back gate voltage range where a part of the back interface is not depleted over the whole subthreshold region, depending on the front gate voltage, which influences strongly the determination of the subthreshold slope, resulting in a non-abrupt transient region. It is proposed a method for extracting the interface trap density in gate oxide/silicon film and silicon film/buried oxide interfaces minimizing the influence of the back accumulation layer in the subthreshold slope with the back interface accumulated. This method was also applied experimentally.

Analog parameters on pMOS SOI Ω-gate nanowire down to 10 nm width for different back gate bias

This paper shows for the first time, the influence of back gate bias (VB) in some analog parameters on pMOS Silicon-On-Insulator (SOI) omega-gate nanowire (ΩG-NW) devices down to 10 nm width (W). An excellent electrostatic control is observed in devices down to 40 nm of channel length. The saturated transconductance slightly increase while the output conductance slightly decrease with VB increment, resulting in an increase of intrinsic voltage gain (AV) up to 30% for wider devices.

Influence of the Tunneling Gate Current on C-V Curves

This paper presents a study of the tunneling gate current influence on the Capacitance vs. Voltage curve in deep submicrometer CMOS technology. Two-dimensional numerical simulations are performed considering thin gate oxide and N+ polysilicon as a gate material. The influence of the tunneling gate current on the polysilicon depletion region is also analysed. It is observed that the tunneling current masks the polysilicon depletion effect due to the large increase of the substrate silicon depletion region.

Physical and Electrical Characterization of Thin Nickel Films Obtained from Electroless Plating onto Aluminum

In this work, nickel was deposited onto smooth aluminum surfaces using the electroless plating technique, which is selective, does not consume surface and does not need an external current source. Before electroless nickel deposition, the aluminum surface was previously covered using a nickel displacement solution. Physical and electrical characterization of the Ni/Al structure was performed with the aid of Rutherford Backscattering Spectrometry (RBS), Atomic Force Microscopy (AFM), Scanning Electron Microscopy (SEM) and C-V measurements. For the C-V measurements, MOS capacitors were fabricated using basic microelectronics steps. During the displacement reaction in solution 0.1 M NiCl 2 /0.1 M HF/0.108 M NH 4 F, aluminum was partially consumed and the surface RMS microroughness gradually increased from 16.8 to 129.8 nm after immersion from 0 to 45 s, respectively. The surface RMS microroughness slightly increased to 133.1 nm after electroless plating for 180 s in solution 0.063 M NiCl 2 /0.09 M Na 2 H 2 PO 2 /0.2 M (NH 4 )HC 6 H 5 O 7 /0.1 M NH 4 OH at 85 °C. As a result, a final nickel thickness of 307 nm and small grains with diameter of approximately 0.5 μm were obtained. In conclusion, electroless plating onto aluminum with a good control can be used as an alternative Ni bumping base for Al bondpads without substantial lateral corrosion. Also, the electrical characteristics of the Ni/Al/SiO 2 /Si structure did not substantially deteriorate (especially the flat hand voltage shift was lower than 0.15 V).