Tapobrata Bandyopadhyay

Electrical modeling of Through Silicon and Package Vias

This paper presents analytical modeling and 3D full-wave electromagnetic (EM) simulation of the bias voltage dependent semiconductor (MOS) capacitance of a Through Silicon Via (TSV). An accurate electrical model of the TSV is proposed by considering the semiconductor effects. The high-frequency electrical performance of TSVs and Through-Package Vias (TPVs) are compared by means of 3D EM simulations. A parametric study is performed on TSV capacitance and design guidelines are presented for signal and power TSVs.

Low-Cost Thin Glass Interposers as a Superior Alternative to Silicon and Organic Interposers for Packaging of 3-D ICs

Interconnecting integrated circuits (ICs) and 3-D-ICs to the system board (printed circuit board) are currently achieved using organic or silicon-based interposers. Organic interposers face several challenges in packaging 2-D and 3-D-ICs beyond the 32-nm node, primarily due to their poor dimensional stability and coefficient of thermal expansion (CTE) mismatch to silicon. Silicon interposers made with back-end of line wafer processes can achieve the required wiring and I/O density, but their high-cost limit them to high-performance applications. Glass is proposed as a superior alternative to organic and silicon-based interposers for packaging of future ICs and 3-D-ICs with highest I/Os at lowest cost. This paper presents for the first time a novel thin and large panel glass interposer capable of scaling to 700 mm and larger panels with potential for significant cost reduction over interposers made on 200-mm or 300-mm wafers. The formation of small through vias at high speed has been the biggest technical barrier for the adoption of glass as an interposer and system substrate; and this paper describes pioneering research in via-formation in thin glass substrates, using a novel “polymer-on-glass” approach. Electrical modeling and design of through package vias (TPVs) in glass is discussed in detail, and the feasibility of 50-μm pitch TPVs in 180-μm thin glass substrates has been demonstrated. The excellent surface finish and low CTE of glass leads to increased I/O density, and increased functionality per unit area leading to system miniaturization.

Through-package-via formation and metallization of glass interposers

Interposer technology has evolved from ceramic to organic materials and most recently to silicon. Organic substrates exhibit poor dimensional stability, thus requiring large capture pads which make them unsuitable for very high I/Os with fine pitch interconnections. Therefore, there has been a trend to develop silicon interposers. Silicon interposers however, suffer in two ways; 1) they are expensive to process due to the need for electrical insulation around via walls, and 2) they are limited in size by the silicon wafer from which they originate. In this paper, glass is proposed as a superior alternative interposer technology to address the limitations of both silicon and organic interposers. The inherent electrical properties of glass, together with large area panel size availability, make it superior compared to organic and silicon-based interposers. Glass however, is not without its challenges. It suffers in two ways: 1) formation of vias at low cost, and 2) its lower thermal conductivity compared to silicon. This research explores glass as an interposer material, and addresses the above key challenges in through package via (TPV) formation and subsequent low cost and large area metallization to achieve very high I/Os at fine pitch.

Electromagnetic Modeling of Through-Silicon Via (TSV) Interconnections Using Cylindrical Modal Basis Functions

This paper proposes an efficient method to model through-silicon via (TSV) interconnections, an essential building block for the realization of silicon-based 3-D systems. The proposed method results in equivalent network parameters that include the combined effect of conductor, insulator, and silicon substrate. Although the modeling method is based on solving Maxwells equation in integral form, the method uses a small number of global modal basis functions and can be much faster than discretization-based integral-equation methods. Through comparison with 3-D full-wave simulations, this paper validates the accuracy and the efficiency of the proposed modeling method.

Rigorous Electrical Modeling of Through Silicon Vias (TSVs) With MOS Capacitance Effects

3-D integration of microelectronic systems reduces the interconnect length, wiring delay, and system size, while enhancing functionality by heterogeneous integration. Through silicon via (TSV) is a key building block for high-performance 3-D systems. This paper presents an accurate electrical modeling of TSVs considering metal-oxide-semiconductor (MOS) capacitance effects. The model is correlated with measurement results for validation. Parametric analysis of TSV capacitance is performed on several physical and material parameters. Design guidelines are proposed for TSVs used in signal and power distribution networks as well as for TSVs as variable capacitors. A 3-D power distribution network is simulated to show the effect and importance of the voltage-dependent TSV MOS capacitance.

Design, fabrication and characterization of low-cost glass interposers with fine-pitch through-package-vias

This paper demonstrates thin glass interposers with fine pitch through package vias (TPV) as a low cost and high I/O substrate for 3D integration. Interposers for packaging of ULK and 3D-ICs need to support large numbers of die to die interconnections with I/O pitch below 50 μm. Current organic substrates are limited by CTE mismatch, wiring density, and poor dimensional stability. Wafer based silicon interposers can achieve high I/Os at fine pitch, but are limited by high cost. Glass is an ideal interposer material due to its insulating property, large panel availability and CTE match to silicon. The main focus of this work is on a) electrical and mechanical design, b) TPV and fine line formation and c) integration process and electrical characterization of thin glass interposers. This work for the first time demonstrates high throughput formation of 30 μm pitch TPVs in ultrathin glass using a parallel laser process. An integration process was demonstrated for glass interposer with polymer build-up layers on both sides. The glass interposer had stable electrical properties up to 20GHz and low insertion loss of less than 0.15dB was measured for TPVs at 9GHz.

Trend from ICs to 3D ICs to 3D systems

Moores Law has driven the IC industry to a billion transistor chip. But major technical and financial barriers are foreseen beyond 32 nm. One alternative path to this challenge seems to be stacked 3D ICs. But 3D ICs are a small part of any system and the total benefits of miniaturization cannot be realized until the entire system is miniaturized. This is the basis of 3D systems, the focus of this paper. The 3D miniaturization technologies briefly described in this paper include Si or wafer level interposers with Through-Package-Vias (TPV), nano-scale passives, thermal materials and interfaces and fine pitch system interconnections.

Ultra-high I/O density glass/silicon interposers for high bandwidth smart mobile applications

Smart mobile applications are driving the demand for higher logic-to-memory bandwidth (BW) in 10–30 GB/s range with lower power consumption and larger memory capacity. This paper presents a radically-different, scalable and lower cost approach than the 3D ICs with TSV stack approach being pursued widely, to achieve high bandwidth. This approach is referred to as interposer approach using ultra-thin glass or silicon with ultra-high I/O density interposers, which does not require TSVs in the logic IC in the 3D stack. This paper presents a comparative study, based on electrical modeling of the logic-to-memory signal path, in various current and emerging package configurations for use in smart mobile devices. Frequency and time domain analysis for each of these scenarios is performed using both chip and package-level models with varying interconnection dimensions. Simulated eye diagrams for the complete data paths in the thin glass interposer approach demonstrated more than 3 Gbps/pin data rate, similar to 3D ICs.

Design and demonstration of low cost, panel-based polycrystalline silicon interposer with through-package-vias (TPVs)

This paper for the first time proposes and demonstrates the use of panel-based polycrystalline silicon interposers for highest I/Os at lowest cost. Such an interposer is targeted at roughly a 10× lower cost compared to wafer based silicon interposers with through silicon vias (TSVs) and back end of line (BEOL) re-distribution layers (RDL). Laser via ablation was used to demonstrate through package vias (TPVs) as small as 10μm diameter in 220μm thin polycrystalline silicon panels made without any chemical-mechanical polishing (CMP). A thick polymer via liner and stress buffer layer was formed in the silicon TPVs to replace oxide liners and diffusion barriers used in TSVs. A panel silicon interposer test vehicle process demonstrator was fabricated and initial electrical measurements indicate much lower loss compared to CMOS silicon interposer with thin oxide liners. Electrical and mechanical design and modeling was also carried out to provide design guidelines for TPV formation.

Electrical modeling of annular and co-axial TSVs considering MOS capacitance effects

This paper presents analytical modeling and parametric study of the voltage dependent metal-oxide-semiconductor (MOS) capacitance of annular and co-axial TSVs. 3D electromagnetic (EM) simulations of TSVs are performed considering the depletion region. A low loss TSV structure is proposed utilizing the MOS capacitance effect.