Vinayak Rastogi

Towards electrical testable SOI devices using Directed Self-Assembly for fin formation

The first fully integrated SOI device using 42nm-pitch directed self-assembly (DSA) process for fin formation has been demonstrated in a 300mm pilot line environment. Two major issues were observed and resolved in the fin formation process. The cause of the issues and process optimization are discussed. The DSA device shows comparable yield with slight short channel degradation which is a result of a large fin CD when compared to the devices made by baseline process. LER/LWR analysis through the DSA process implied that the 42nm-pitch DSA process may not have reached the thermodynamic equilibrium. Here, we also show preliminary results from using scatterometry to detect DSA defects before removing one of the blocks in BCP.

TRENCH AND HOLE PATTERNING WITH EUV RESISTS USING DUAL FREQUENCY CAPACITIVELY COUPLED PLASMA (CCP)

Patterning at 10 nm and sub-10 nm technology nodes is one of the key challenges for the semiconductor industry. Several patterning techniques are under investigation to enable the aggressive pitch requirements demanded by the logic technologies. EUV based patterning is being considered as a serious candidate for the sub-10nm nodes. As has been widely published, a new technology like EUV has its share of challenges. One of the main concerns with EUV resists is that it tends to have a lower etch selectivity and worse LER/LWR than traditional 193nm resists. Consequently the characteristics of the dry etching process play an increasingly important role in defining the outcome of the patterning process. In this paper, we will demonstrate the role of the dual-frequency Capacitively Coupled Plasma (CCP) in the EUV patterning process with regards to improving LER/LWR, resist selectivity and CD tunability for holes and line patterns. One of the key knobs utilized here to improve LER and LWR, involves superimposing a negative DC voltage in RF plasma at one of the electrodes. The emission of ballistic electrons, in concert with the plasma chemistry, has shown to improve LER and LWR. Results from this study along with traditional plasma curing methods will be presented. In addition to this challenge, it is important to understand the parameters needed to influence CD tunability and improve resist selectivity. Data will be presented from a systematic study that shows the role of various plasma etch parameters that influence the key patterning metrics of CD, resist selectivity and LER/LWR. This work was performed by the Research Alliance Teams at various IBM Research and Development Facilities.

Implementation of atomic layer etching of silicon: Scaling parameters, feasibility, and profile control

Atomic or layer by layer etching of silicon exploits temporally segregated self-limiting adsorption and material removal steps to mitigate the problems associated with continuous or quasicontinuous (pulsed) plasma processes: selectivity loss, damage, and profile control. Successful implementation of atomic layer etching requires careful choice of the plasma parameters for adsorption and desorption steps. This paper illustrates how process parameters can be arrived at through basic scaling exercises, modeling and simulation, and fundamental experimental tests of their predictions. Using chlorine and argon plasma in a radial line slot antenna plasma source as a platform, the authors illustrate how cycle time, ion energy, and radical to ion ratio can be manipulated to manage the deviation from ideality when cycle times are shortened or purges are incomplete. Cell based Monte Carlo feature scale modeling is used to illustrate profile outcomes. Experimental results of atomic layer etching processes are illustr...

Driving DSA into volume manufacturing

Directed Self-Assembly (DSA) is being extensively evaluated for application in semiconductor process integration.1-7 Since 2011, the number of publications on DSA at SPIE has exploded from roughly 26 to well over 80, indicating the groundswell of interest in the technology. Driving this interest are a number of attractive aspects of DSA including the ability to form both line/space and hole patterns at dimensions below 15 nm, the ability to achieve pitch multiplication to extend optical lithography, and the relatively low cost of the processes when compared with EUV or multiple patterning options. Tokyo Electron Limited has focused its efforts in scaling many laboratory demonstrations to 300 mm wafers. Additionally, we have recognized that the use of DSA requires specific design considerations to create robust layouts. To this end, we have discussed the development of a DSA ecosystem that will make DSA a viable technology for our industry, and we have partnered with numerous companies to aid in the development of the ecosystem. This presentation will focus on our continuing role in developing the equipment required for DSA implementation specifically discussing defectivity reduction on flows for making line-space and hole patterns, etch transfer of DSA patterns into substrates of interest, and integration of DSA processes into larger patterning schemes.

Evaluation of novel processing approaches to improve extreme ultraviolet (EUV) photoresist pattern quality

Recently there has been a great deal of effort focused on increasing EUV scanner source power; which is correlated to increased wafer throughput of production systems. Another way of increasing throughput would be to increase the photospeed of the photoresist used. However increasing the photospeed without improving the overall lithographic performance, such as local critical dimension uniformity (L-CDU) and process window, does not deliver the overall improvements required for a high volume manufacturing (HVM). This paper continues a discussion started in prior publications [Ref 3,4,6], which focused on using readily available process tooling (currently in use for 193 nm double patterning applications) and the existing EUV photoresists to increase photospeed (lower dose requirement) for line and space applications. Techniques to improve L-CDU for contact hole applications will also be described.

Fin formation using graphoepitaxy DSA for FinFET device fabrication

A 27nm-pitch Graphoepitaxy directed self-assembly (DSA) process targeting fin formation for FinFET device fabrication is studied in a 300mm pilot line environment. The re-designed guiding pattern of graphoepitaxy DSA process determines not only the fine DSA structures but also the fin customization in parallel direction. Consequently, the critical issue of placement error is now resolved with the potential of reduction in lithography steps. However, challenges in subsequent pattern transfer are observed due to insufficient etch budget. The cause of the issues and process optimization are illustrated. Finally, silicon fins with 100nm depth in substrate with pre-determined customization is demonstrated.

Plasma etch patterning of EUV lithography: balancing roughness and selectivity trade off

EUV based patterning is one of the frontrunner candidates enabling scaling for future technology nodes. However it poses the common challenges of ‘pattern roughness’ and ‘etch resistance’ aspect which are getting even more critical as we work on smaller dimension features. Continuous efforts are ongoing to improve resist materials and lithography process but the industry is slowly moving to introduce it at high volume manufacturing. Plasma Etch processes have the potential to improvise upon the incoming pattern roughness and provide improved LER/LWR downstream to expedite EUV progress. In this work we demonstrate the specific role of passivation control in the dualfrequency Capacitively Coupled Plasma (CCP) for EUV patterning process with regards to improving LER/LWR, resist selectivity and CD tunability for line/space patterns. We draw the implicit commonalities between different passivation chemistry and their effectiveness for roughness improvement. The effect of relative C:F and C:H ratio in feed gas on CFx and CHx plasma species and in turn the evolution of pattern roughness is drawn. Data that shows the role of plasma etch parameters impacting the key patterning metrics of CD, resist selectivity and LER/LWR is presented.

Etch considerations for directed self-assembly patterning using capacitively coupled plasma

Alternative patterning strategies are pursued to push the device feature size below the physical limit of optical lithography as the semiconductor manufacturing industry is preparing for production at sub-10 nm technology node. Extreme ultraviolet (EUV) lithography, 193 nm immersion augmented with multiple patterning schemes (“self-aligned double patterning,” “self-aligned quadruple patterning”) and “directed self-assembly (DSA)” are being evaluated as alternatives to meet rising demands of aggressive patterning. EUV lithography reduces the number of processing steps, but it is yet to achieve full maturity in terms of resist materials, throughput, and manufacturability. DSA when augmented with 193 nm immersion guide prepatterns can aid in reducing the pitch of final structures. There is no infrastructure upgrade cost involved as the key processing steps of DSA are conducted in existing wafer track systems. The authors have successfully demonstrated DSA pattern transfer into metal hard masks for the back e...

Plasma etch challenges for next-generation semiconductor manufacturing

In the photolithography process, a requisite mask layout is printed into a polymer layer. This layer, in turn, is transferred onto underlying inorganic/organic material layers for the fabrication of 3D semiconductors, and for high-volume integrated-chip manufacturing. Moore’s law describes a trend, first observed in 1965, in which the dimension of patterns in these layouts shrinks every two years, doubling the number of transistors on the microchip. Optical lithography has long since reached its physical limit (i.e., printing feature sizes below 40nm), and a number of alternative printing/material deposition schemes have been evaluated for use below this limit (see Figure 1) to maintain the economy of scaling. Among these schemes, plasma etching (which transfers the printed mask layout onto underlying layers by initiating chemical reactions) is employed industrywide. Plasma is partially ionized gas (i.e., which contains gas atoms/molecules, activated radicals, and ions). The dry plasma etching process involves interactions—between radicals and the exposed surface—which lead to the removal/volatilization of the activated/modified layer via energetic ion bombardment. To optimize the etch process, the pressure, gas flow/flow ratios, radio frequency power, and substrate temperature can be modified by adjusting the appropriate tuning knobs. When one of these tuning knobs is adjusted, change is triggered in more than one of the plasma parameters (i.e., the radical flux, ion flux, ion energy, and ion energy distribution). In a continuous plasma-etch process, surface modification (activation) and energetic material removal (desorption) occur concurrently. Concurrence is problematic, however, because changing plasma parameters to improve one aspect of the printed mask transfer may degrade Figure 1. Alternative patterning schemes able to achieve feature sizes of less than 40nm: 193nm immersion lithography combined with selfaligned multiple patterning; extreme UV (EUV) lithography; and directed self-assembly (DSA). Each color represents a different material layer. SADP: Self-aligned double patterning. SAQP: Self-aligned quadruple patterning. SAOP: Self-aligned octuple patterning.1

Dual frequency mid-gap capacitively coupled plasma (m-CCP) for conventional and DSA patterning at 10nm node and beyond

In this paper, we demonstrate the unique advantage of dual-frequency mid-gap capacitively coupled plasma (m-CCP) in advanced node patterning process with regard to etch rate / depth uniformity and critical dimension (CD) control in conjunction with wider process window for aspect ratio dependent & microloading effects. Unlike the non-planar plasma sources, the simple design of the mid-gap CCPs enables both metal and non-metal hard-mask based patterning, which provides essential flexibility for conventional and DSA patterning. We present data on both, the conventional multi patterning as well as DSA patterning for trenches / fins and holes. Rigorous CD control and CDU is shown to be crucial for multi patterning as they lead to undesirable odd-even delta and pitch walking. For DSA patterning, co-optimized Ne / Vdc of the dual frequency CCPs would be demonstrated to be advantageous for higher organic-to-organic selectivity during co-polymer etching.