Vincent Etienne Houtsma

Highly Efficient Harmonically Tuned InP D-HBT Push-Push Oscillators Operating up to 287 GHz

Integrated push-push oscillators, achieving high output power at 210, 235 and 287 GHz, were realized in a 0.5 mum emitter double-heterojunction InGaAs/InP HBT (D-HBT) technology with a maximum oscillation frequency fmax of 335 GHz and a breakdown voltage (Vbceo) of 4 V. The oscillators are based on a balanced Colpitts topology in which a strong second harmonic signal is generated by combining the differential signals at the collector and by reactively tuning the output impedance of the oscillator using a shorted stub. Three oscillators were realized using this topology. A high-power output signal of more then 0 dBm is obtained for oscillators operating at 210 and 232 GHz, an improvement of 5 dB compared to the output power measured on an identical push-push oscillator without 2nd harmonic tuning. Close to -3 dBm output power is obtained at an output frequency of 280 GHz by further reducing the resonator length. By reducing the current, a maximum output frequency of 287 GHz is obtained.

Single ended to differential MHEMT transimpedance amplifier with 66 dB-/spl Omega/ differential transimpedance and 50 GHz bandwidth

In this paper, we demonstrate a single ended to differential transimpedance amplifier (TIA) with 66 dB/spl Omega/ transimpedance gain, a 50 GHz 3-dB bandwidth and up to 700 mVp-p differential output voltage, fabricated in a 6-inch MHEMT process. The state-of-the-art gain-bandwidth product of this amplifier (>3 THz), combined with its small chip size (1.9/spl times/1.1 mm/sup 2/), high sensitivity and low power consumption (<350 mW) demonstrate the capabilities of a lumped MHEMT TIA design to realize a low cost receiver for 40 Gb/s fiber optic communication systems.

Fully dry-etched InP Double-Hetero Bipolar Transistors with ft > 400 GHz

Indium Phosphide-based Double-Heterostructure Bipolar Transistors have high potential for analog, digital, and mixed-signal applications requiring extreme clock speed and high voltage swing. To harness the full performance of the InGaAs/InP material system, the HBTs need to be scaled to submicron dimensions. Yield has always been an issue with wet-etch defined submicron InP HBTs. More complex circuits require homogeneous and reproducible processing techniques. We demonstrate a manufacturable InP HBT technology which relies on dry etching of all three semiconductor mesas (emitter, base, and subcollector), thus greatly improving control of critical dimensions and device parameters such as Cbc, Cbe, and collector current at which maximumft and fmax are attained. Further, we replaced the traditional emitter metal liftoff patterning process by dryetched refractory metal. When scaling the emitter area, the emitter resistance increases inversely with the emitter size, requiring reduction of the specific emitter resistance. Dry etching of the emitter contact metal and the underlying semiconductor allows for a straight edge of the emitter contact, as opposed to wet etching: the crystallographic etching of InGaAs leaves a pyramidal shape, reducing the contact area, and inhibiting scaling of the emitter size. We achieved total emitter resistance as low as 5 Q for an emitter junction area of 0.5 x 4 jtm2(extracted from S-parameter measurements). Dry etching of the base mesa allows for a tight base layout, keeping Cbc low from the onset. For our highest performance devices, we dry etched the base and part of the collector, followed by a selective wet etch of InP to reduce the base-collector capacitance. In this setup, the vertical and lateral etches can be tailored independently. Minimum Cbc of 5.5 fF was recorded for HBTs with 0.5 x 4 ptm emitter geometry. Thirdly, the subcollector is defined by a mesa dry etch. The use of dry etch processing allows for a tight HBT layout, allowing dense HBT device packing. InP is used as a subcollector material owing to the superior thermal properties of InP as compared to InGaAs. The subcollector etch is terminated based on a laser interferometer signal, indicating the point where the etch reaches the semi-insulating InP substrate. This method is reliable enough to forgo any InGaAs etch stop layers, lowering the total thermal resistance of the device. The vertical dry etching in InP and InGaAs is based on extensive development work of hightemperature inductively coupled plasma etching. BC13, C12, and N2 are used as etch gases. The role ofN2 is to reduce the removal rate of phosphorus and arsenic compounds, respectively. As a result, smooth vertical surfaces and smooth trenches are obtained. The etch rate in the high-temperature regime well above the temperature where InCl becomes volatile (about 1 70°C) is very well defined from run to run over many months. The measured data and the extracted device model do not show detrimental impact of the dry etches on the ideality factors, leakage currents, and current gain. This device technology has been proven in InP HBT MMICs including broadband amplifiers, static dividers, and push-push oscillators, with more than 130 GHz bandwidth.

High Gain-Bandwidth InP waveguide Phototransistor

We present a high speed phototransistor with integrated waveguide based on our InP double hetrojunction bipolar transistor (DHBT) process technology. We measured an optical-gain cutoff frequency F,* of 447 GHz with an internal optical gain of over gePt=30 at a base current of It.=650 pA using devices with emitter dimensions of A=0.7 x 4 pm2.

Recent Advances in III-V Electronics

Compound III-V semiconductor circuits promise fast and power efficient analog, digital and mixed-mode applications. This paper provides an overview of recent advances in high speed III-V compound devices and integrated circuits for high capacity wireless and optic fiber communications. Several critical compound semiconductor ASIC technologies and their unique performance advantages over prevailing silicon CMOS and SiGe technologies will be illustrated