Vincent Kerzerho

Fast Digital Post-Processing Technique for Integral Nonlinearity Correction of Analog-to-Digital Converters: Validation on a 12-Bit Folding-and-Interpolating Analog-to-Digital Converter

The semiconductor industry tends to constantly increase the performances of developed systems with an ever-shorter time-to-market. In this context, the conventional strategy for mixed-signal component design, which is based only on analog design effort, will no longer be suitable. In this paper, a digital correction technique is presented for analog-to-digital converters (ADCs). The idea is to use a lookup table (LUT) for the online correction of integral nonlinearity (INL). The main challenge for this kind of technique is the cost in time and resources to estimate the actual INL of the ADC needed to load the LUT. In this paper, we propose to extract INL with a very rapid procedure based on spectral analysis. We validate our technique on a 12-bit folding-and-interpolating ADC and we demonstrate that the correction is efficient for a large range of application fields.

Efficiency evaluation of analog/RF alternate test

The conventional practice for testing analog or RF integrated circuits is specification-based testing, which relies on the direct measurement of the circuit performance parameters. This approach offers good test quality but at the price of extremely high testing costs. In order to reduce test costs, a promising approach, called indirect or alternate testing has been proposed. Its basic principle consists in using the correlation between the conventional analog/RF performances and some low-cost measurements, called Indirect Measurements (IMs), in order to estimate the analog/RF parameters without measuring them directly. In this paper, we perform efficiency evaluation of this strategy, and in particular we perform a comparative analysis of different IM selection strategies in order to define efficient alternate testing implementation. Efficiency is evaluated in terms of model accuracy by using classical metrics such as average and maximal prediction errors, and in terms of prediction reliability by introducing a new metric called Failing Prediction Rate (FPR). Results are illustrated on two case studies for which we have experimental test data.

A First Step for an INL Spectral-Based BIST: The Memory Optimization

Integral non-linearity (INL) is the main static parameter of analog-to-digital converter. This paper presents a comparison between different INL test techniques based on INL estimation from the spectrum of the converted signal. The most common technique is based on polynomial fitting of the INL curve. This technique is well suited to the estimation of a smooth INL curve without sharp transitions. The new method described in the paper is based on a Fourier series expansion of the INL curve. We demonstrate that this new technique allows a more efficient INL estimation. The comparison between the two techniques has been realized thanks to a metrics that considers the uncertainty of production test measurements. Finally, we propose a first step of the study of implementation feasibility of the INL estimation technique. This study focus only on the optimization of required memory.

A novel implementation of the histogram-based technique for measurement of INL of LUT-based correction of ADC

The histogram-based technique is commonly used for testing of Analog-to-Digital Converters (ADC). One of the parameters measured thanks to this technique is the Integral Non Linearity (INL). INL is also used as an initial data related to the ADC performances for the computation of a correction table in case of a LUT-based correction technique. In this context of embedded INL measurement and embedded computation of the table for LUT-based correction of ADC, we propose a new implementation establishing what we consider the best trade-off between silicon area overhead and computing time. We compare our solution with the state of the art: (a) with VHDL-level simulation we compare time performance, and (b) with FPGA placer we estimate the final surface head-out.

On the Use of Redundancy to Reduce Prediction Error in Alternate Analog/RF Test

Specification testing, which involves the direct measurement of the circuit performance parameters is the conventional practice for testing analog/RF devices. While this approach is highly accurate, it often incurs extremely high testing costs. A promising approach is to adopt alternate test strategy, i.e. a strategy in which test results are derived from indirect low-cost measurements. The underlying idea is to learn during a training phase the mapping between indirect measurements and circuit performance parameters, and to use only indirect measurements to predict device specifications during production testing. Despite the substantial test cost reduction offered by this strategy, its deployment in industry is today limited, mainly because confidence in alternate test predictions is difficult to assess. In this paper, we propose a novel implementation with the objective to improve confidence in alternate test predictions. The idea is to exploit model redundancy in order to identify, during the production testing phase, devices with suspect predictions and remove these devices from the alternate test flow. This approach is illustrated on a real case study for which we have experimental measurements on a set of 10,000 devices.

ADC production test technique using low-resolution arbitrary waveform generator

Standard production test techniques for ADC require an ATE with an arbitrary waveform generator (AWG) with a resolution at least 2 bits higher than the ADC under test resolution. This requirement is a real issue for the new high-performance ADCs. This paper proposes a test solution that relaxes this constraint. The technique allows the test of ADC harmonic distortions using only low-cost ATE. The method involves two steps. The first step, called the learning phase, consists in extracting the harmonic contributions from the AWG. These characteristics are then used during the second step, called the production test, to discriminate the harmonic distortions induced by the ADC under test from the ones created by the generator. Hardware experimentations are presented to validate the proposed approach.

Evaluation of indirect measurement selection strategies in the context of analog/RF alternate testing

This paper is in the field of Analog or RF integrated circuit testing. The conventional practice for testing those circuits relies on the measurement of the device-under-test (DUT) specifications. In order to reduce test costs, a promising approach, called indirect or alternate testing has been proposed. Its basic principle consists in using the correlation between the conventional analog/RF performances and some low-cost measurements, called Indirect Measurements (IMs), in order to estimate the analog/RF parameters without measuring directly them. The objective of this paper is to perform a comparative analysis of different IM selection strategies in order to define efficient alternate testing implementation. Efficiency is discussed in terms of model accuracy and predictions robustness. Results are illustrated on a Power Amplifier (PA) test vehicle for which we have experimental test data on 10,000 circuits.

Analytical study of on-chip generations of analog sine-wave based on combined digital signals

On-chip sine-wave signal generation is widely covered by literature for Built-In-Self Test (BIST) or biosensor applications. The objective is to generate pure and robust sinewave signal with minimal hardware resources. An attractive solution consists in combining several digital signals to built this analog sine-wave. The objective of this paper is to give an analytical study of various potential solutions based on digitalbased approaches. Thanks to this study, we prove that technique consisting in setting the phase shifts and various amplitude values of the square-wave signals is the most efficient approach. Moreover, this study allows the selection of the best solution in terms of parameters of the square-wave signals to cancel loworder harmonics of the generated signal.

Solutions for the self-adaptation of communicating systems in operation

In the context of mission-critical, safety-critical, and remote-controlled applications, it is required to equip systems with self-adapting capabilities. Adaptation is required in post-manufacturing to correct yield loss and achieve zero defective parts-per-million as well as during normal operation to account for different application scenarios and for varying environmental conditions. A self-adaptive system must be capable of providing the required high performances after manufacturing and throughout its normal operation regardless the application scenario wherein it is deployed and despite the varying environmental conditions. In this paper, we describe a generic post-manufacturing self-adaptation technique for RF circuits as well as concurrent self-adaptation techniques for a safety-critical medical sensor for glaucoma diagnosis and for a NFC system which is very sensitive to the environment in which it operates.

Accurate and efficient analytical electrical model of antenna for NFC applications

An accurate, compact, efficient analytical model at the electrical level of antennas dedicated to NFC (Near Field Communication) applications is presented in this paper. The model takes into account the skin effect, which is usually neglected in existing electrical models while it constitutes a major issue in the NFC context. The proposed model is validated with respect to finite element simulation. Comparison with most significant state-of-the-art models proves the proposed analytical model to be more accurate and efficient for antenna modeling in the NFC context.